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Line 232:
Line 232: − When writing to the AES_CTR, AES_MAC or AES_KEY0/1/2/3 register, the hardware will process the written data according to the current input endianness specified in AES_CNT. This means that the byte ordering within each word is endian swapped accordingly but the word ordering of the register remains little endian.+ + + + + + + + + + + + + + + +
Clarify endianness and word order docs
== Endianness and word order ==
== Endianness and word order ==
=== AES_CNT.input_endianness ===
Swaps the bytes of 32-bit writes to AES_CTR, AES_WRFIFO, AES_KEY*FIFO according to specified endianness. AES_MAC?
=== AES_CNT.output_endianness ===
Swaps the bytes of 32-bit reads from AES_RDFIFO.
=== AES_CNT.input_word_order ===
If reversed, writes to AES_KEY*FIFO and AES_WRFIFO fill the FIFO backwards. For AES_WRFIFO, this means that every 16-byte block will have its words in the reverse order, but the order of these blocks remains the same. AES_CNT is unaffected by this field. AES_MAC?
=== AES_CNT.output_word_order ===
If reversed, reads from AES_RDFIFO will drain the FIFO backwards. This means that every 16-byte output block will have its words in the reverse order, but the order of these blocks remains the same.
== CCM mode pitfall ==
== CCM mode pitfall ==