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→Trigger Memory Fill: control bits
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|-
| 7
| 7
| The low u16 is width0, while the high u16 is width1 (?)
| The low u16 is control0, while the high u16 is control1
|}
|}
This commands converts the specified addresses to physical addresses, then writes these addresses and the specified parameters to the [[GPU]] registers at 0x1EF00010 and 0x1EF00020. Doing so fills the specified buffers with the associated 4-byte value. This is used to clear GPU framebuffers.
This commands converts the specified addresses to physical addresses, then writes these addresses and the specified parameters to the [[GPU]] registers at 0x1EF00010 and 0x1EF00020. Doing so fills the specified buffers with the associated 4-byte value. This is used to clear GPU framebuffers.
The associated buffer address must not be <= to the main buffer address, thus the associated buffer address must not be zero as well. When the bufX address is zero, processing for the bufX parameters is skipped.
The associated buffer address must not be <= to the main buffer address, thus the associated buffer address must not be zero as well. When the bufX address is zero, processing for the bufX parameters is skipped.
The values of control0 and control1 give information about the type of memory fill and if it has to be triggered. By default the fill pattern is set to 16bits.
{| class="wikitable" border="1"
|-
! Bit
! Description
|-
| 0
| trigger
|-
| 8
| Fill pattern of 24bits
|-
| 9
| Fill pattern of 32bits
|}
== Trigger Display Transfer ==
== Trigger Display Transfer ==