SHA Registers

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Old3DS Name Address Width Used by
Yes SHA_CNT 0x1000A000 4 Boot9, Process9
Yes SHA_BLKCNT 0x1000A004 4 Process9
Yes SHA_HASH 0x1000A040 0x20 Process9
Yes SHA_FIFO 0x1000A080 0x40 Boot9, Process9


Bits Description
0 Start (1=enable/busy, 0=idle)
1 Final round (1=enable/busy, 0=normal)
2 Input DMA enable (1= enable, 0=disable)
3 Output Endianess (0=little, 1=big)
4-5 Mode (0=SHA256, 1=SHA224, 2=3=SHA1)
6 ?
7 ?
8 Clear FIFO? When set, the *entire* ARM9 hangs/crashes when attempting to read SHA_INFIFO.
9 Enable FIFO (1=fifo, 0=write-only)
10 Output DMA enable (1= enable, 0=disable)
16 ?
17 ?

Bit 8 is used when boot9 chains eMMC reads with AES and SHA to to load, decrypt and verify FIRM partitions.


This reg contains the total size of the data written to REG_SHA_IN, this field is updated when performing hash-function final-round.


This reg contains the SHA* hash after the final round, and the internal state during normal rounds. It is possible to write the internal state using this register.


The data to be hashed must be written here. It does not matter what offset is written to.