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Created page with "== Registers == {| class="wikitable" border="1" ! NAME ! PHYSICAL ADDRESS ! WIDTH |- | REG_SHA_CNT | 0x1000A000 | 4 |- | ?? | 0x1000A004 | 4 |- | REG_SHA_OUT | 0x1000A040 | 0x..."
== Registers ==
{| class="wikitable" border="1"
! NAME
! PHYSICAL ADDRESS
! WIDTH
|-
| REG_SHA_CNT
| 0x1000A000
| 4
|-
| ??
| 0x1000A004
| 4
|-
| REG_SHA_OUT
| 0x1000A040
| 0x20
|-
| REG_SHA_IN
| 0x1000A080
| 0x40
|}
== REG_SHACNT ==
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| 0=Hash ready, 1=Normal, 2=Final Round
|-
| 16
| Enable
|-
| 17
| 1 when FIFO expects read/write
|}
{| class="wikitable" border="1"
! NAME
! PHYSICAL ADDRESS
! WIDTH
|-
| REG_SHA_CNT
| 0x1000A000
| 4
|-
| ??
| 0x1000A004
| 4
|-
| REG_SHA_OUT
| 0x1000A040
| 0x20
|-
| REG_SHA_IN
| 0x1000A080
| 0x40
|}
== REG_SHACNT ==
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| 0=Hash ready, 1=Normal, 2=Final Round
|-
| 16
| Enable
|-
| 17
| 1 when FIFO expects read/write
|}