6,264
edits
Changes
Jump to navigation
Jump to search
Line 132:
Line 132: + + + + + + + + + + + + + + + + + + + + + + + + +
no edit summary
FFFFB000 - FFFFE000: mapped L2 MMU tables (1FFF5000 - 1FFF8000)
FFFFB000 - FFFFE000: mapped L2 MMU tables (1FFF5000 - 1FFF8000)
==0xFF4XX000==
Each [[KThread|thread]] is allocated a 0x1000-byte page in this region: the first page at 0xFF401000 is for the first created thread, 0xFF403000 for the second thread. This region is used to store the SVC-mode stack for the thread, and thread context data used for context switching. When the IRQ handler, prefetch/data abort handlers, and undefined instruction handler are entered where the SPSR-mode=user, these handlers then store LR+SPSR for the current mode on the SVC-mode stack, then these handlers switch to SVC-mode.
This page does not contain a dedicated block for storing R0-PC(etc). For user-mode, the user-mode regs are instead saved on the SVC-mode stack when IRQs such as timers for context switching are triggered.
Structure of this page, relative to page_endaddr-0xC8:
{| class="wikitable" border="1"
|-
! Offset
! Size
! Description
|-
| 0x0
|
| SVC-mode stack-top
|-
| 0x18
| 0x28
| SVC-mode saved registers, stored/loaded during context switches: R4-R9, SL, FP, SP, LR. After loading these registers, the context switch code will jump to the loaded LR.
|-
| 0xC0
| 4
| fpexc from vmrs, used during context switches with the above saved registers.
|}
=ARM11 User-land memory regions=
=ARM11 User-land memory regions=