Normally this register is all-zero, however bit2 in this register is set by the ARM11 kernel when ARM debug CP14 DSCR bit14 is set. [[NS]] loads the menu TID from MENUTID when bits 1-7 of this register are clear. | Normally this register is all-zero, however bit2 in this register is set by the ARM11 kernel when ARM debug CP14 DSCR bit14 is set. [[NS]] loads the menu TID from MENUTID when bits 1-7 of this register are clear. |