Line 1: |
Line 1: |
− | == Registers ==
| + | = Registers = |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
− | ! NAME | + | ! Old3DS |
− | ! PHYSICAL ADDRESS | + | ! Name |
− | ! WIDTH | + | ! Address |
| + | ! Width |
| + | ! Used by |
| |- | | |- |
− | | REG_CTRCARDCNT | + | | style="background: green" | Yes |
| + | | [[#CTRCARD_CNT|CTRCARD_CNT]] |
| | 0x10004000 | | | 0x10004000 |
| | 4 | | | 4 |
| + | | Process9 |
| |- | | |- |
− | | REG_CTRCARDSECCNT | + | | style="background: green" | Yes |
| + | | [[#CTRCARD_BLKCNT|CTRCARD_BLKCNT]] |
| + | | 0x10004004 |
| + | | 4 |
| + | | Process9 |
| + | |- |
| + | | style="background: green" | Yes |
| + | | [[#CTRCARD_SECCNT|CTRCARD_SECCNT]] |
| | 0x10004008 | | | 0x10004008 |
| | 4 | | | 4 |
| + | | Process9 |
| |- | | |- |
− | | REG_CTRCARDSECSEED | + | | style="background: green" | Yes |
| + | | CTRCARD_SECSEED |
| | 0x10004010 | | | 0x10004010 |
| | 4 | | | 4 |
| + | | Process9 |
| |- | | |- |
− | | REG_CTRCARDCMD | + | | style="background: green" | Yes |
| + | | [[#CTRCARD_CMD|CTRCARD_CMD]] |
| | 0x10004020 | | | 0x10004020 |
| | 16 | | | 16 |
| + | | Process9 |
| |- | | |- |
− | | REG_CTRCARDFIFO | + | | style="background: green" | Yes |
| + | | CTRCARD_FIFO |
| | 0x10004030 | | | 0x10004030 |
| | 4 | | | 4 |
| + | | Process9 |
| |} | | |} |
| | | |
− | == REG_CTRCARDCNT == | + | == CTRCARD_CNT == |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
− | ! BIT | + | ! Bit |
− | ! DESCRIPTION | + | ! Description |
| + | |- |
| + | | 3-0 |
| + | | ? |
| + | |- |
| + | | 4 |
| + | | CRC status (1=Error, 0=OK)? |
| + | |- |
| + | | 15-5 |
| + | | ? |
| + | |- |
| + | | 19-16 |
| + | | Transfer size (0=0 bytes, 1=4 bytes, 2=0x10 bytes, 0x40, 0x200, 0x400, 0x800, 0x1000, 8=0x4000 bytes) |
| + | |- |
| + | | 23-20 |
| + | | ? |
| + | |- |
| + | | 26-24 |
| + | | Clock delay (0..5) |
| + | |- |
| + | | 27 |
| + | | Data ready (1=Ready, 0=Busy) |
| + | |- |
| + | | 28 |
| + | | Reset (1=High, 0=Low) |
| + | |- |
| + | | 29 |
| + | | Transfer mode (1=Write, 0=Read) |
| + | |- |
| + | | 30 |
| + | | Interrupt enable (1=Enable, 0=Disable) |
| |- | | |- |
| | 31 | | | 31 |
Line 35: |
Line 83: |
| |} | | |} |
| | | |
− | == REG_CTRCARDCMD == | + | === Remarks === |
| + | Once reset is set high, it cannot be changed until controller is reset. |
| + | |
| + | == CTRCARD_BLKCNT == |
| + | {| class="wikitable" border="1" |
| + | ! Bit |
| + | ! Description |
| + | |- |
| + | | 15-0 |
| + | | Total data blocks to read from FIFO - 1 |
| + | |- |
| + | | 31-16 |
| + | | Total data blocks to write to FIFO - 1 |
| + | |} |
| + | |
| + | == CTRCARD_SECCNT == |
| + | {| class="wikitable" border="1" |
| + | ! Bit |
| + | ! Description |
| + | |- |
| + | | 2 |
| + | | Latch key index |
| + | |- |
| + | | 9-8 |
| + | | Key index |
| + | |- |
| + | | 15 |
| + | | Latch seed |
| + | |} |
| + | |
| + | == CTRCARD_CMD == |
| Specifies the 16-byte command to send. The command is split into 32-bit words, and stored as least significant word first, with each word itself in big-endian format. | | Specifies the 16-byte command to send. The command is split into 32-bit words, and stored as least significant word first, with each word itself in big-endian format. |