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Line 92: − + + − + + + + + − The command buffer is located at sharedmem + 0x800 + [[GSPGPU:RegisterInterruptRelayQueue|threadindex]]*0x200. After writing the command data to shared memory, [[GSPGPU:TriggerCmdReqQueue|TriggerCmdReqQueue]] must be used to trigger GSP processing for the command when the total commands field is value 1.+ Line 99:
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Line 132: − + − + + + + − + − + − + − + − The command is located at cmdbuf + 0x20 + cmdindex*0x20, the size of each command is 0x20-bytes. The command parameters are located at command+4. Addresses specified in parameters are application vaddrs, these are usually located in either the process GSP [[Memory_layout|heap]] or VRAM. For applications these addresses are normally located in the GSP heap, while for other processes these addresses are located in VRAM. Addresses/sizes specified in parameters except for cmd0 and cmd5 must be 8-byte [[GPU|aligned]].+ + + + + − + − == Trigger DMA Request == Line 162:
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no edit summary
This page describes the structure of the GSP [[GSPGPU:RegisterInterruptRelayQueue|shared]] memory. GX commands and framebuffer info is stored here, and other unknown data.
This page describes the structure of the GSP [[GSPGPU:RegisterInterruptRelayQueue|shared]] memory. Interrupt, framebuffer, and GX command data is stored here.
=Interrupt Queue=
The Interrupt queue is located at sharedMemBase + (clientID * 0x40).
The Interrupt info structure is located at sharedmemvadr + process_gsp_index*0x40.
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PDC interrupts are sent to all processes; other interrupts are only sent to the process with GPU rights.
PDC interrupts are sent to all processes; other interrupts are only sent to the process with GPU rights.
=Framebuffer info=
= Framebuffer Info =
The framebuffer info structure for the main LCD is located at sharedmemvadr + 0x200 + threadindex*0x80. The framebuffer info structure for the sub LCD is located at sharedmemvadr + 0x240 + threadindex*0x80.
The framebuffer info structure for the top LCD is located at sharedMemBase + 0x200 + (clientID * 0x80).
The framebuffer info structure for the bottom LCD is located at sharedMemBase + 0x240 + (clientID * 0x80).
== Framebuffer Info Header ==
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==Framebuffer info structure==
== Framebuffer Info Structure ==
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The two 0x1C-byte framebuffer info entries are located at framebufferinfo+4.
The two 0x1C-byte framebuffer info entries are located at framebufferinfo+4.
=3D Slider and 3D [[GSPGPU:SetLedForceOff|LED]]=
= 3D Slider and 3D [[GSPGPU:SetLedForceOff|LED]] =
See [[Configuration Memory]].
See [[Configuration Memory]].
=Command Buffer Header=
= Command Queue =
The command queue is located at sharedMemBase + 0x800 + (clientID * 0x200). It consists of an header followed by at most 15 command entries. Each command entry is of size 0x20 and has an header followed by command specific parameters.
After adding a command, [[GSPGPU:TriggerCmdReqQueue|TriggerCmdReqQueue]] must be used to trigger GSP processing when the total commands field is value 1.
== Command Queue Header ==
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! Description
! Description
|-
|-
| 0
| 0
| Current command index. This index is updated by GSP module after loading the command data, right before the command is processed. When this index is updated by GSP module, the total commands field is decreased by one as well.
| Index of the command to process, this is incremented by GSP before handling the command
|-
|-
| 1
| 1
| Total commands to process, must not be value 0 when GSP module handles commands. This must be <=15 when writing a command to shared memory. This is incremented by the application when writing a command to shared memory, after increasing this value [[GSPGPU:TriggerCmdReqQueue|TriggerCmdReqQueue]] is only used if this field is value 1.
| Total commands to process, this is incremented by the application when adding the command to the queue, and decremented by GSP before handling the command
|-
|-
| 2
| 2
| Must not be value 1. When the error-code u32 is set, this u8 is set to value 0x80.
| Flags (bit0 = completed?, bit7 = fatal error)
|-
|-
| 3
| 3
| Bit0 must not be set
| ? (bit0 = set flags.bit0)
|-
|-
| 4
| 4
| u32 Error code for the last GX command which failed
| Result code for the last GX command which failed
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=Command Header=
== Command Header ==
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|-
|-
! Description
! Description
|-
|-
| 0
| 0
| Command ID
| Command ID
|-
| 1
| ?
|-
|-
| 2-1
| 2
| ?
| ? (bit0 = set queue.flags.bit0 after processing)
|-
|-
| 3
| 3
| When non-zero GSP module may check flags for the specified cmdID, command handling is aborted when the flags are set. The corresponding flag for each CmdID is set once the command is handled by GSP module, this flag is likely cleared once the GPU finishes processing the command.
| When set, the command fails if GSP is busy handling any other command; otherwise, it only fails if GSP is busy handling a command of the same kind
|}
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== Commands ==
Addresses specified in parameters are virtual addresses. For applications these are normally located in GSP memory, while for other processes they are located in VRAM.
Address and size parameters except for command 0 and command 5 must be 8-byte aligned.
=Commands=
=== Trigger DMA Request ===
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This command is normally used to DMA data from the application GSP [[Memory_layout|heap]] to VRAM. When flushing is enabled and the source buffer is not located within VRAM, svcFlushProcessDataCache is used to flush the source buffer.
This command is normally used to DMA data from the application GSP [[Memory_layout|heap]] to VRAM. When flushing is enabled and the source buffer is not located within VRAM, svcFlushProcessDataCache is used to flush the source buffer.
== Trigger Command List Processing ==
=== Trigger Command List Processing ===
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This command converts the specified address to a physical address, then writes the physical address and size to the [[GPU]] registers at 0x1EF018E0. This buffer contains [[GPU/Internal_Registers|GPU commands]]. When flushing is enabled, svcFlushProcessDataCache is used to flush the buffer.
This command converts the specified address to a physical address, then writes the physical address and size to the [[GPU]] registers at 0x1EF018E0. This buffer contains [[GPU/Internal_Registers|GPU commands]]. When flushing is enabled, svcFlushProcessDataCache is used to flush the buffer.
== Trigger Memory Fill ==
=== Trigger Memory Fill ===
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The values of Control0 and Control1 give information about the type of memory fill. See [[GPU/External_Registers#Memory Fill|here]] for more information about memory fill parameters.
The values of Control0 and Control1 give information about the type of memory fill. See [[GPU/External_Registers#Memory Fill|here]] for more information about memory fill parameters.
== Trigger Display Transfer ==
=== Trigger Display Transfer ===
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Some color formats seem to require specific input / output sizes when performing a display transfer, doing an RGB5A1->RGBA4 display transfer would never fire the PPF interrupt with a 32x32 buffer, increasing the buffer to 128x128 made it fire correctly.
Some color formats seem to require specific input / output sizes when performing a display transfer, doing an RGB5A1->RGBA4 display transfer would never fire the PPF interrupt with a 32x32 buffer, increasing the buffer to 128x128 made it fire correctly.
== Trigger Texture Copy ==
=== Trigger Texture Copy ===
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This command is similar to cmd3. It also triggers the [[GPU/External_Registers#Transfer_Engine|GPU Transfer Engine]], but setting the TextureCopy parameters.
This command is similar to cmd3. It also triggers the [[GPU/External_Registers#Transfer_Engine|GPU Transfer Engine]], but setting the TextureCopy parameters.
== Flush Cache Regions ==
=== Flush Cache Regions ===
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