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=Interrupt info=
=Interrupt info=
The Interrupt info structure is located at sharedmemvadr + process_gsp_index*0x40.
The Interrupt info structure is located at sharedmemvadr + process_gsp_index*0x40.
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0x0
| 0x0
| Index of the last processed data (must be updated manually)
| Offset from the count where to save incoming interrupts
|-
|-
| 0x1
| 0x1
| Count (max 0x1F for PDC, 0x33 for others)
| Count (max 0x20 for PDC, 0x34 for others)
|-
|-
| 0x2
| 0x2
| Missed other interrupts (set to 1 when 0 and count > 0x33)
| Missed other interrupts (set to 1 when 0 and count >= 0x34)
|-
|-
| 0x3
| 0x3
|-
|-
| 0x4-0x7
| 0x4-0x7
| Missed PDC0 (incremented when flags.bit0 is clear and count > 0x1F)
| Missed PDC0 (incremented when flags.bit0 is clear and count >= 0x20)
|-
|-
| 0x8-0xB
| 0x8-0xB
| Interrupt list (u8) (0=PSC0, 1=PSC1, 2=PDC0/VBlankTop, 3=PDC1/VBlankBottom, 4=PPF, 5=P3D, 6=DMA)
| Interrupt list (u8) (0=PSC0, 1=PSC1, 2=PDC0/VBlankTop, 3=PDC1/VBlankBottom, 4=PPF, 5=P3D, 6=DMA)
|}
|}
GSP fills the interrupt list, then triggers the event set with [[GSPGPU:RegisterInterruptRelayQueue|RegisterInterruptRelayQueue]] for the specified process(es).
PDC interrupts are sent to all processes; other interrupts are only sent to the process with GPU rights.
PDC interrupts are sent to all processes; other interrupts are only sent to the process with GPU rights.