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Line 148:
Line 148: − 0x10 --> 0x14 --> 0x18 --> 0x60 low --> 0x04 --> 0x60 high --> 0x08 --> 0x0C. + + + Line 154:
Line 156: − + − + Line 185:
Line 187: − + − + + + − + − + + + − + − + + + + + + + Line 277:
Line 289: − + − + − +
Adding new PDC reg names and descriptions (continuation)
The horizontal timing parameter order is as follows:
The horizontal timing parameter order is as follows:
10 < 14 <= 60.LO <= 04 <= 60.HI <= 08 <= 0C
18 <= 60.LO
Timing starts from HCount == 0, then each absolute value in the beforementioned register chain triggers when HCount == register, latching the primitive display controller into a new mode.
Timing starts from HCount == 0, then each absolute value in the beforementioned register chain triggers when HCount == register, latching the primitive display controller into a new mode.
There is an inherent latch order, where if two simultenaous events occur, one event wins over another.
There is an inherent latch order, where if two simultenaous events occur, one event wins over another.
Known latched modes (in no particular order):
Known latched modes (in no particular order):
- HSync (triggers a line to the LCD to move to the next line)
- HSync (triggers a line to the LCD to move to the next line)
- Back porch (area between HSync and border being displayed)
- Back porch (area between HSync and border being displayed, min 16 pixel clocks, otherwise the screen gets glitchy)
- Left border start (no image data is being displayed, just a configurable solid color)
- Left border start (no image data is being displayed, just a configurable solid color)
- Image start (pixel data is being DMA'd from video memory or main RAM)
- Image start (pixel data is being DMA'd from video memory or main RAM)
- Right border start/Image end (border color is being displayed after the main image)
- Right border start/Image end (border color is being displayed after the main image)
- Front porch (unknown where it happens)
- Front porch (68 clock min, otherwise the screenn doesn't sync properly, and really glitches out)
- Unknown synchronization/blanking (unknown where it happens)
- Unknown synchronization/blanking (unknown where it happens)
|-
|-
| 0x10
| 0x10
| HParam1
| HSync
|
| Triggers a HSync pulse.
Based on behavior, this needs to last at least a pixel clock for the LCD to register the sync.
|-
|-
| 0x14
| 0x14
| HParam2
| HPB
|
| Back porch? Has to be at least one bigger than HSync, otherwise HSync never triggers.
The display is blank, and the LCD displays nothing in this period (doesn't push pixels).
|-
|-
| 0x18
| 0x18
| HParam3
| HBL
|
| Left border trigger treshold.
If this value is smaller than the back porch, then the back porch period will be zero, and the border will be immediately displayed upon entering the back porch period.
Can be lower than HSync, as the back porch is what takes the controller out of HSync.
Must be <= HDisp start (reg 0x60 low u16).
|-
|-
| 0x1C
| 0x1C
|-
|-
| 0x60
| 0x60
| ???
| HDisp
| low u16: HParam4
| low u16: Image start (border --> pixel data)
high u16: HParam6
high u16: Image end (pixel data --> border)
|-
|-
| 0x64
| 0x64