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Line 321: − + − Bit0: main (?) nRESET (active low), unset to reset (when not on reset, external GPU registers at 0x10400000+ are enabled). − When this is unset VRAM is not accessible and triggers exceptions. − Bit0: Enable VRAM clock in older models??+ + + + + + + − + + + + + + + + + + + + Line 332:
Line 362: − + + + + + + + + + + + + + + + − Kernel11 uses it before going to sleep. It does a dummy read before touching this reg.+ − This is the power register used for the [[PDN_Services|PDN]] camera service.+ + + + + + + − bit0 = unknown, bit1 = turn on/off cameras, rest = always 0.+ + + + + + + + + + + + + − + − This is the power register used for the [[PDN_Services|PDN Services]] DSP service.+ + + + + + + − bit0: NRESET (active low). Unset to reset/hold reset.+ − bit1: enable bit. − PDN services holds reset for 0x30 Arm11 cycles.+ +
Cleanup
= Registers =
=Register table=
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Old3DS
! Old3DS
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#PDN_SLEEP_CNT|PDN_SLEEP_CNT]]
| [[#PDN_CNT|PDN_CNT]]
| 0x10141000
| 0x10141000
| 2
| 2
| [[#PDN_VRAM_CNT|PDN_VRAM_CNT]]
| [[#PDN_VRAM_CNT|PDN_VRAM_CNT]]
| 0x10141204
| 0x10141204
| 4
| 1
| Boot11, Kernel11, TwlBg
| Boot11, Kernel11, TwlBg
|-
| style="background: green" | Yes
| [[#PDN_LCD_CNT|PDN_LCD_CNT]]
| 0x10141208
| 1
| Boot11
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| [[#PDN_CODEC_CNT|PDN_CODEC_CNT]]
| [[#PDN_I2S_CNT|PDN_I2S_CNT]]
| 0x10141220
| 0x10141220
| 1
| 1
| 1
| 1
| Process9, [[PDN Services]]
| Process9, [[PDN Services]]
|-
| style="background: red" | No
| [[#PDN_MVD_CNT|PDN_MVD_CNT]]
| 0x10141240
| 1
|
|-style="border-top: double"
|-style="border-top: double"
| style="background: red" | No
| style="background: red" | No
|}
|}
==PDN_SLEEP_CNT==
=Sleep registers=
==PDN_CNT==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Bits
For each bit, write 1 to acknowledge, and 0 to clear (?).
For each bit, write 1 to acknowledge, and 0 to clear (?).
=Legacy registers=
==LGY_MODE==
==LGY_MODE==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
See above
See above
=Clock and reset registers=
==PDN_GPU_CNT==
==PDN_GPU_CNT==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0
| 0
| GPU External register block reset. 0 = reset.
| GPU main block + VRAM + LCD reset. 0 = reset.
|-
|-
| 1
| 1
|-
|-
| 16
| 16
| Clock enable for all blocks and VRAM. 1 = enable.
| Clock enable for all blocks, VRAM and LCD. 1 = enable.
|}
|}
PDN uses a 12 ARM11 cycle delay to deassert reset.
PDN uses a 12 ARM11 cycle delay to deassert reset.
==PDN_VRAM_CNT==
==PDN_VRAM_CNT==
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Clock. 1 = enable, 0 = disable
|}
This register seems to be unimplemented in released models: while it is used in tandem with PDN_GPU_CNT.bit16 in boot11 screeninit code, Kernel11 only uses PDN_GPU_CNT.bit16 to put VRAM in self-refresh mode.
This register seems to be unimplemented in released models: while it is used in tandem with PDN_GPU_CNT.bit16 in Boot11 screeninit code, Kernel11 only uses PDN_GPU_CNT.bit16 to power-off VRAM before going to sleep.
==PDN_LCD_CNT==
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Clock. 1 = enable, 0 = disable
|}
This register seems to be unimplemented in released models, only to be used in Boot11, as PDN_GPU_CNT.bit16 also drives the LCD clock.
==PDN_FCRAM_CNT==
==PDN_FCRAM_CNT==
| Acknowledge clock request. Gets set or unset when toggling bit 1.
| Acknowledge clock request. Gets set or unset when toggling bit 1.
|}
|}
Twl-/AgbBg use this to disable FCRAM for the GBA rom in GBA mode or DSi main RAM in DSi mode. Agb-/TwlBg clears bit 0 in reg 0x10201000 before touching this reg.
Twl-/AgbBg use this to disable FCRAM for the GBA rom in GBA mode or DSi main RAM in DSi mode. AgbBg clears bit 0 in reg 0x10201000 before touching this reg.
Kernel11 uses it to put the FCRAM in self-refresh mode (clock disable) before going to sleep.
==PDN_I2S_CNT==
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| I2S1 Clock (maybe?) 1 = enable, 0 = disable
|-
| 1
| I2S2 Clock. 1 = enable, 0 = disable
|}
I2S1 clock enable bit seems to be unimplemented. Maybe it's because DSP clock enable drives it?
==PDN_CAMERA_CNT==
==PDN_CAMERA_CNT==
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Clock. 1 = enable, 0 = disable
|}
==PDN_DSP_CNT==
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Reset. 0 = reset.
|-
| 1
| Clock. 1 = enable, 0 = disable
|}
PDN services holds reset for 0x30 Arm11 cycles.
==PDN_DSP_CNT==
==PDN_MVD_CNT==
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Reset. 0 = reset
|}
This doesn't seem to be used by anything, but does have a clear effect on the hardware.
The reset value for this register is 1 (out-of-reset at boot).
=N3DS SoC (LGR) registers=
== PDN_LGR_SOCMODE ==
== PDN_LGR_SOCMODE ==
This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read.
This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read.