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Line 388:
Line 388: − + − + − + + + +
→PDN_MPCORE_SOCMODE
Possible values:
Possible values:
0=O3DS (2 cores, 256MHz)
0=O3DS (2 cores, 256MHz)
1=N3DS (LGR2?, 4 cores, 256MHz), 5=N3DS (LGR2?, 4 cores, 804MHz)
1=LGR2+256MHz, 5=LGR2+804MHz
2=N3DS prototype (LGR, 2 cores, 256MHz), 3=N3DS prototype (LGR, 2 cores, 536MHz)
2=LGR+256MHz, 3=LGR+536MHz
N3DS modes enable the New 3DS FCRAM extension and are needed to access N3DS-only devices.
N3DS modes (LGR1/LGR2) enable the New 3DS FCRAM extension and are needed to access N3DS-only devices.
* LGR1: N3DS prototype, 2 cores, no L2C
* LGR2: retail N3DS, 4 cores, has L2C
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