Line 32: |
Line 32: |
| |- | | |- |
| | style="background: green" | Yes | | | style="background: green" | Yes |
− | | ? | + | | [[#CFG9_XDMA_CNT|CFG9_XDMA_CNT]] |
| | 0x10000008 | | | 0x10000008 |
| | 1 | | | 1 |
Line 62: |
Line 62: |
| |- | | |- |
| | style="background: green" | Yes | | | style="background: green" | Yes |
− | | [[#CFG9_SDSLOTCTL|CFG9_SDSLOTCTL]] | + | | [[#CFG9_SDMMCCTL|CFG9_SDMMCCTL]] |
| | 0x10000020 | | | 0x10000020 |
| | 2 | | | 2 |
Line 161: |
Line 161: |
| |} | | |} |
| | | |
− | == 0x10000008 == | + | == CFG9_XDMA_CNT == |
| + | |
| + | Write 1 to enable XDMA for the device, 0 to disable. Always enabled for CTRCARD (ids 0 and 1), NTRCARD (id 8), and SHA (id 6 for infifo and 7 for outfifo). |
| + | |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Bit | | ! Bit |
Line 167: |
Line 170: |
| ! Used by | | ! Used by |
| |- | | |- |
− | | 1-0 | + | | 0 |
− | | ? | + | | SDIO controller 1 (eMMC and usually SD card; XDMA device ID: 2) |
| + | | |
| + | |- |
| + | | 1 |
| + | | SDIO controller 3 (SD card if configured so; ID: 3) |
| | | | | |
| |- | | |- |
− | | 3-2 | + | | 2 |
− | | AES related? Value 3 written after write to AES_CTL. | + | | AES Input FIFO (ID: 4) |
| + | | Boot9, Process9, TwlProcess9 |
| + | |- |
| + | | 3 |
| + | | AES Output FIFO (ID: 5) |
| | Boot9, Process9, TwlProcess9 | | | Boot9, Process9, TwlProcess9 |
| |- | | |- |
Line 191: |
Line 202: |
| |- | | |- |
| | 8 | | | 8 |
− | | Enable gamecard eject IRQ, maybe? | + | | 1 = Switch to [[SPICARD_Registers|SPICARD]] interface (savegames). |
| | Process9 | | | Process9 |
| |} | | |} |
Line 211: |
Line 222: |
| |- | | |- |
| | 3-2 | | | 3-2 |
− | | ? | + | | Cartridge-slot power supply (0=off, 1=prepare power regulator, 2=enable output, 3=request power down) |
| | Process9 | | | Process9 |
| |} | | |} |
| | | |
− | == CFG9_SDSLOTCTL == | + | When the power supply is in the "request power down" state, the power bits will be reset to 0=off after some time. |
− | CFG9_SDSLOTCTL controls power and SD card detect?
| + | |
| + | == CFG9_SDMMCCTL == |
| + | This register controls power of multiple ports/controllers and allows to map controller 3 to ARM9 or ARM11. The SD card can be accessed on ARM11 by setting bit 8 and clearing bit 9. |
| | | |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
Line 223: |
Line 236: |
| ! Used by | | ! Used by |
| |- | | |- |
− | | 0-3 | + | | 0 |
− | | Powers on the SD card slot when unset. Each bit does the same? | + | | Controller 1/3 port 0 power (SD card) (1=off) |
| | Process9 | | | Process9 |
| + | |- |
| + | | 1 |
| + | | Controller 1 port 1 power (eMMC) (1=off) |
| + | | Process9 |
| + | |- |
| + | | 2 |
| + | | Controller 2 port 0 power (WiFi SDIO) (1=off) |
| + | | Process9 |
| + | |- |
| + | | 3 |
| + | | Controller 3 port 1 power? Set at cold boot. |
| + | | - |
| + | |- |
| + | | 4-5 |
| + | | Unused. |
| + | | - |
| + | |- |
| + | | 6 |
| + | | Wifi port related? Pull up? Set at cold boot. |
| + | | - |
| |- | | |- |
| | 8 | | | 8 |
− | | ? This bit seems to do nothing. | + | | Controller 3 mapping (0=ARM9 0x10007000, 1=ARM11 0x10100000) |
| | Process9 | | | Process9 |
| |- | | |- |
| | 9 | | | 9 |
− | | Enables SD card detection? | + | | SD card controller select (0=0x10007000/0x10100000, 1=0x10006000) |
| | Process9 | | | Process9 |
| + | |- |
| + | | 10-15 |
| + | | Unused. |
| + | | - |
| |} | | |} |
| | | |