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|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| ARM11 interrupt related.
| [[#PDN_FIQ_CNT|PDN_FIQ_CNT]]
| 0x10140104
| 0x10140104
| 1
| 1
| Enable (0=Disable, 1=Enable)
| Enable (0=Disable, 1=Enable)
|}
|}
== PDN_FIQ_CNT ==
Writing bit1 to this register disables (?) FIQ interrupts.
This bit is set upon receipt of a FIQ interrupt and when [[SVC|svcUnbindInterrupt]] is called on the FIQ-abstraction [[ARM11_Interrupts#Private_Interrupts|software interrupt]] for the current core.
It is cleared when binding that software interrupt to an event and after such an event is signaled.
== PDN_SPI_CNT ==
== PDN_SPI_CNT ==