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Line 5,818:
Line 5,818: + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + − The format the current depth buffer should be written into. Following values are possible:+ + + + + + + + + Line 5,835:
Line 5,905: − |- − | 1 − | ?? seems to freeze the GPU Line 5,843:
Line 5,910: − + − Describes the format of the current color buffer used for 3D rendering.+ + + + + + + + + + + + − + − + − + − + − + − Note that these values are slightly different from those in [[GPU#Framebuffer_color_formats]].+ + + − Color components are laid out in reverse byte order, with the most significant bits used first.+ + + + + + + + + + + + + + + Line 5,876:
Line 5,970: − When set to 0, use regular 8x8 tiling format for the framebuffer, compatible with textures. When set to 1, use a 32x32 tiling format. To untile the color buffer when using this format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
→Framebuffer registers
=== GPUREG_FRAMEBUFFER_INVALIDATE ===
=== GPUREG_FRAMEBUFFER_INVALIDATE ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Trigger (0 = idle, 1 = invalidate)
|}
Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.
Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.
=== GPUREG_FRAMEBUFFER_FLUSH ===
=== GPUREG_FRAMEBUFFER_FLUSH ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Trigger (0 = idle, 1 = flush)
|}
Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.
Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.
=== GPUREG_COLORBUFFER_READ ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Allow read (0 = disable, 0xF = enable)
|}
=== GPUREG_COLORBUFFER_WRITE ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| Allow write (0 = disable, 0xF = enable)
|}
=== GPUREG_DEPTHBUFFER_READ ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Allow stencil read (0 = disable, 1 = enable)
|-
| 1
| Allow depth read (0 = disable, 1 = enable)
|}
=== GPUREG_DEPTHBUFFER_WRITE ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Allow stencil write (0 = disable, 1 = enable)
|-
| 1
| Allow depth write (0 = disable, 1 = enable)
|}
=== GPUREG_DEPTHBUFFER_FORMAT ===
=== GPUREG_DEPTHBUFFER_FORMAT ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| Format
|}
Format values:
{| class="wikitable" border="1"
{| class="wikitable" border="1"
| 0
| 0
| 16-bit depth
| 16-bit depth
|-
|-
| 2
| 2
|-
|-
| 3
| 3
| 24-bit depth + 8-bit stencil (stencil is within bit 24-31)
| 24-bit depth + 8-bit stencil
|}
|}
=== GPUREG_COLORBUFFER_FORMAT ===
=== GPUREG_COLORBUFFER_FORMAT ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| Pixel size
|-
| 16-18
| Format
|}
Pixel size values:
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Value
! Description
! Description
|-
|-
| 0-7
| 0
| Pixel size (0=16-bit, 1=24-bit, 2=32-bit, 3=64-bit?)
| 16-bit color
|-
|-
| 16-23
| 2
| Framebuffer Format (0=GL_RGBA8, 1=GL_RGB8, 2=GL_RGB5_A1, 3=GL_R5_G6_B5, 4=GL_RGBA4).
| 32-bit color
|}
Format values:
{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| RGBA8/Gas
|-
| 2
| RGB5A1
|-
| 3
| RGB565
|-
| 4
| RGBA4
|}
|}
=== GPUREG_FRAMEBUFFER_BLOCK32 ===
=== GPUREG_FRAMEBUFFER_BLOCK32 ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Render block mode
|}
To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.
Render block mode values:
{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 8x8 blocks
|-
| 1
| 32x32 blocks
|}
=== GPUREG_DEPTHBUFFER_LOC ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| Depth buffer physical address >> 3
|}
=== GPUREG_COLORBUFFER_LOC ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| Color buffer physical address >> 3
|}
=== GPUREG_FRAMEBUFFER_DIM ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| Width
|-
| 12-21
| Height
|}
=== GPUREG_FRAGOP_SHADOW ===
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float16, Sum of penumbra scale and penumbra bias
|-
| 16-31
| float16, Penumbra scale with reversed sign
|}
== Fragment lighting registers ==
== Fragment lighting registers ==