Line 71:
Line 71:
| [[Y2R:SetSendingYUYV|SetSendingYUYV]]
| [[Y2R:SetSendingYUYV|SetSendingYUYV]]
|-
|-
−
| 0x0014....
+
| 0x00140000
−
| WaitForSendingDmaFinishY
+
| IsBusySendingY(bool * state)
|-
|-
−
| 0x0015....
+
| 0x00150000
−
| WaitForSendingDmaFinishU
+
| IsBusySendingU(bool * state)
|-
|-
−
| 0x0016....
+
| 0x00160000
−
| WaitForSendingDmaFinishV
+
| IsBusySendingV(bool * state)
|-
|-
−
| 0x0017....
+
| 0x00170000
−
| WaitForSendingDmaFinishYUYV
+
| IsBusySendingYUYV(bool * state)
|-
|-
| 0x00180102
| 0x00180102
| SetReceiving(unsigned int pDst, unsigned int imageSize, short transferUnit, short transferStride, 0, Handle dstProcess).
| SetReceiving(unsigned int pDst, unsigned int imageSize, short transferUnit, short transferStride, 0, Handle dstProcess).
|-
|-
−
| 0x0019....
+
| 0x00190000
−
| WaitForReceivingDmaFinish
+
| IsBusyReceiving(bool * state)
|-
|-
| 0x001A0040
| 0x001A0040