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no edit summary
== Registers ==
== Registers ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! NAME
! Old3DS
! PHYSICAL ADDRESS
! Name
! WIDTH
! Address
! Width
! RW
! RW
|-
|-
| REG_AESCNT
| [[#AES_CNT|AES_CNT]]
| 0x10009000
| 0x10009000
| 4
| 4
| RW
| RW
|-
|-
| REG_AESBLKCNT
| [[#AES_BLKCNT|AES_BLKCNT]]
| 0x10009004
| 0x10009004
| 4
| 4
| W?
| W?
|-
|-
| REG_AESWRFIFO
| [[#AES_WRFIFO/AES_RDFIFO|AES_WRFIFO]]
| 0x10009008
| 0x10009008
| 4
| 4
| W
| W
|-
|-
| REG_AESRDFIFO
| [[#AES_WRFIFO/AES_RDFIFO|AES_RDFIFO]]
| 0x1000900C
| 0x1000900C
| 4
| 4
| R
| R
|-
|-
| REG_AESKEYSEL
| AES_KEYSEL
| 0x10009010
| 0x10009010
| 1
| 1
| RW
| RW
|-
|-
| REG_AESKEYCNT
| [[#AES_KEYCNT|AES_KEYCNT]]
| 0x10009011
| 0x10009011
| 1
| 1
| RW
| RW
|-
|-
| REG_AESCTR
| [[#AES_CTR|AES_CTR]]
| 0x10009020
| 0x10009020
| 16
| 16
| W
| W
|-
|-
| REG_AESMAC
| [[#AES_MAC|AES_MAC]]
| 0x10009030
| 0x10009030
| 16
| 16
| W
| W
|-
|-
| REG_AESKEY0
| AES_KEY0
| 0x10009040
| 0x10009040
| 48
| 48
| W
| W
|-
|-
| REG_AESKEY1
| AES_KEY1
| 0x10009070
| 0x10009070
| 48
| 48
| W
| W
|-
|-
| REG_AESKEY2
| AES_KEY2
| 0x100090A0
| 0x100090A0
| 48
| 48
| W
| W
|-
|-
| REG_AESKEY3
| AES_KEY3
| 0x100090D0
| 0x100090D0
| 48
| 48
| W
| W
|-
|-
| REG_AESKEYFIFO
| AES_KEYFIFO
| 0x10009100
| 0x10009100
| 4
| 4
| W
| W
|-
|-
| REG_AESKEYXFIFO
| AES_KEYXFIFO
| 0x10009104
| 0x10009104
| 4
| 4
| W
| W
|-
|-
| REG_AESKEYYFIFO
| AES_KEYYFIFO
| 0x10009108
| 0x10009108
| 4
| 4
|}
|}
== REG_AESCNT ==
== AES_CNT ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bit
! Bit
Clearing bit31 while the AES engine is doing crypto will result in the AES engine stopping crypto, once it finishes processing the current block.
Clearing bit31 while the AES engine is doing crypto will result in the AES engine stopping crypto, once it finishes processing the current block.
== REG_AESBLKCNT ==
== AES_BLKCNT ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|}
|}
== REG_AESWRFIFO/REG_AESRDFIFO ==
== AES_WRFIFO/AES_RDFIFO ==
Up to 128 bytes of input data can be buffered.
Up to 128 bytes of input data can be buffered.
Reading from REG_AESRDFIFO when there's no data available in the RDFIFO will result in reading the last word that was in the RDFIFO.
Reading from REG_AESRDFIFO when there's no data available in the RDFIFO will result in reading the last word that was in the RDFIFO.
== REG_AESKEYCNT ==
== AES_KEYCNT ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bit
! Bit
Bit6 is only used when keyslots >=4 are used, value1 has the same affect as doing key-init with the TWL keyslots. Bit6 is only checked when a keyY was completely written, for when the final-normalkey needs updated via the key-generator. Changing bit6 has no affect on the generated normalkey when writing to this bit immediately after writing the last keyY word.
Bit6 is only used when keyslots >=4 are used, value1 has the same affect as doing key-init with the TWL keyslots. Bit6 is only checked when a keyY was completely written, for when the final-normalkey needs updated via the key-generator. Changing bit6 has no affect on the generated normalkey when writing to this bit immediately after writing the last keyY word.
== REG_AESCTR ==
== AES_CTR ==
This register specifies the counter (CTR mode), nonce (CCM mode) or the initialization vector (CBC mode) depending on the mode of operation.
This register specifies the counter (CTR mode), nonce (CCM mode) or the initialization vector (CBC mode) depending on the mode of operation.
For CBC and CTR mode this register takes up the full 16 bytes, but for CCM mode the nonce is only the first 12 bytes.
For CBC and CTR mode this register takes up the full 16 bytes, but for CCM mode the nonce is only the first 12 bytes.
== REG_AESMAC ==
== AES_MAC ==
This register specifies the message authentication code (MAC) for use in CCM mode.
This register specifies the message authentication code (MAC) for use in CCM mode.
== Endianness and word order ==
== Endianness and word order ==
When writing to the REG_AESCTR or REG_AESMAC register, the hardware will process the written data according to the current input endianness specified in AESCNT. However, the current specified input word order will not be honored for this register, and always defaults to reversed word order. Therefore, for normal word order, the reversal must be carried out manually if required.
When writing to the AES_CTR or AES_MAC register, the hardware will process the written data according to the current input endianness specified in AES_CNT. However, the current specified input word order will not be honored for this register, and always defaults to reversed word order. Therefore, for normal word order, the reversal must be carried out manually if required.
== Keyslot ranges ==
== Keyslot ranges ==