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Undo revision 11835 by Plutooo (talk)
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== REG_SYSPROT9 ==
−Writing values to SYSPROT sets the specified bitmask. The ARM9 [[Memory_layout|bootrom]](+0x8000) is disabled by writing bit0. bit1 is used by NATIVE_FIRM to make sure console-unique TWL AES-keys are only set at hard-boot. It is not possible to set any other bits.
−From disassembly of the New3DS process9, it appears that setting bit1 disables the 0x10012000+ region.
−== REG_SYSPROT11 ==
−ARM11 bootrom (+0x8000) is disabled by writing bit0. It is not possible to set any other bits.
== REG_BOOTENV ==
−0=Cold boot, 1=CTR, 3=TWL, 7=AGB
−It is unknown if this register controls anything.
|-
|-
| Yes
| Yes
−| REG_CORECONFIG?
+| REG_MPCORECFG?
| 0x10000FFC
| 0x10000FFC
| 4
| 4
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| 1
| 1
|}
|}
+
+== REG_SYSPROT9 ==
+Writing values to SYSPROT sets the specified bitmask. The ARM9 [[Memory_layout|bootrom]](+0x8000) is disabled by writing bit0. bit1 is used by NATIVE_FIRM to make sure console-unique TWL AES-keys are only set at hard-boot. It is not possible to set any other bits.
+
+From disassembly of the New3DS process9, it appears that setting bit1 disables the 0x10012000+ region.
+
+== REG_SYSPROT11 ==
+ARM11 bootrom (+0x8000) is disabled by writing bit0. It is not possible to set any other bits.
== REG_CARDCONF ==
== REG_CARDCONF ==
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* Selecting CTRCARD1 will activate the register space at [[CTRCARD|0x10004000]].
* Selecting CTRCARD1 will activate the register space at [[CTRCARD|0x10004000]].
* Selecting CTRCARD2 will activate the register space at [[CTRCARD|0x10005000]].
* Selecting CTRCARD2 will activate the register space at [[CTRCARD|0x10005000]].
−== REG_EXTMEMCNT9 ==
== REG_EXTMEMCNT9 ==
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The data in this extended memory doesn't change when disabling the memory, then re-enabling the memory. Reading this extended memory while disabled results in zeros.
The data in this extended memory doesn't change when disabling the memory, then re-enabling the memory. Reading this extended memory while disabled results in zeros.
−== 0x10010000 ==
+== REG_BOOTENV ==
Initially this is value zero. NATIVE_FIRM writes value 1 here when a FIRM launch begins. The [[Legacy_FIRM_PXI|LGY]] FIRM writes value 3 here when handling PXI command 0x00020080(first TWL PXI command), it also writes value 7 here when handling PXI command 0x00030080(first AGB PXI command). This register can be read to determine what "mode" the system is running under: hard-boot, FIRM launch, or TWL/AGB FIRM.
Initially this is value zero. NATIVE_FIRM writes value 1 here when a FIRM launch begins. The [[Legacy_FIRM_PXI|LGY]] FIRM writes value 3 here when handling PXI command 0x00020080(first TWL PXI command), it also writes value 7 here when handling PXI command 0x00030080(first AGB PXI command). This register can be read to determine what "mode" the system is running under: hard-boot, FIRM launch, or TWL/AGB FIRM.
+
+0=Cold boot, 1=CTR, 3=TWL, 5=NTR, 7=AGB
+
+It is unknown if this register controls anything.
== REG_UNITINFO ==
== REG_UNITINFO ==
This 8-bit register is value zero for retail, non-zero for dev/debug units.
This 8-bit register is value zero for retail, non-zero for dev/debug units.
−