Line 226:
Line 226:
|}
|}
−
Format 5 : (used for MAD and LRP)
+
Format 5 : (used for MAD)
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
Line 243:
Line 243:
| 0xA
| 0xA
| 0x7
| 0x7
+
| Source 2 register (SRC2)
+
|-
+
| 0x11
+
| 0x7
+
| Source 1 register (SRC1)
+
|-
+
| 0x18
+
| 0x5
+
| Destination register (DST)
+
|-
+
| 0x1D
+
| 0x3
+
| Opcode
+
|}
+
+
Format 5i : (used for MADI)
+
{| class="wikitable" border="1"
+
|-
+
! Offset
+
! Size (bits)
+
! Description
+
|-
+
| 0x0
+
| 0x5
+
| Operand descriptor ID (DESC)
+
|-
+
| 0x5
+
| 0x7
+
| Source 3 register (SRC3)
+
|-
+
| 0xC
+
| 0x5
| Source 2 register (SRC2)
| Source 2 register (SRC2)
|-
|-
Line 503:
Line 535:
|-
|-
| 0x30-0x37
| 0x30-0x37
−
| 5
+
| 5i
−
| LRP
+
| MADI
−
| Does linear interpolation between two vectors, using a third as the interpolation factor, component by component; DST[i] = SRC1[i].(1.0 - SRC3[i]) + SRC2[i].(SRC3[i]) for all i (modulo destination component masking)
+
| Multiplies two vectors and adds a third one component by component; DST[i] = SRC3[i] + SRC2[i].SRC1[i] for all i (modulo destination component masking)
|-
|-
| 0x38-0x3F
| 0x38-0x3F