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GPUREG_*SH_CODE_CONFIG => GPUREG_*SH_CODETRANSFER_CONFIG, GPUREG_*SH_CODETRANSFER_END
There are three main types of registers :
There are three main types of registers :
* configuration registers, which directly map to various rendering properties (for example : [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])
* configuration registers, which directly map to various rendering properties (for example : [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example : [[#GPUREG_GSH_CODE_DATA|GPUREG_GSH_CODE_DATA]])
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example : [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example : [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example : [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])
|-
|-
| 028F
| 028F
| [[#GPUREG_028F|GPUREG_028F]]
| [[#GPUREG_GSH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]
|
|
|-
|-
|-
|-
| 029B
| 029B
| [[#GPUREG_GSH_CODE_CONFIG|GPUREG_GSH_CODE_CONFIG]]
| [[#GPUREG_GSH_CODETRANSFER_CONFIG|GPUREG_GSH_CODETRANSFER_CONFIG]]
| ?
| ?
|-
|-
| 029C
| 029C
| [[#GPUREG_GSH_CODE_DATA|GPUREG_GSH_CODE_DATA]]
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|
|-
|-
| 029D
| 029D
| [[#GPUREG_GSH_CODE_DATA|GPUREG_GSH_CODE_DATA]]
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|
|-
|-
| 029E
| 029E
| [[#GPUREG_GSH_CODE_DATA|GPUREG_GSH_CODE_DATA]]
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|
|-
|-
| 029F
| 029F
| [[#GPUREG_GSH_CODE_DATA|GPUREG_GSH_CODE_DATA]]
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|
|-
|-
| 02A0
| 02A0
| [[#GPUREG_GSH_CODE_DATA|GPUREG_GSH_CODE_DATA]]
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|
|-
|-
| 02A1
| 02A1
| [[#GPUREG_GSH_CODE_DATA|GPUREG_GSH_CODE_DATA]]
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|
|-
|-
| 02A2
| 02A2
| [[#GPUREG_GSH_CODE_DATA|GPUREG_GSH_CODE_DATA]]
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|
|-
|-
| 02A3
| 02A3
| [[#GPUREG_GSH_CODE_DATA|GPUREG_GSH_CODE_DATA]]
| [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]]
|
|
|-
|-
|-
|-
| 02BF
| 02BF
| [[#GPUREG_02BF|GPUREG_02BF]]
| [[#GPUREG_VSH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]
|
|
|-
|-
|-
|-
| 02CB
| 02CB
| [[#GPUREG_VSH_CODE_CONFIG|GPUREG_VSH_CODE_CONFIG]]
| [[#GPUREG_VSH_CODETRANSFER_CONFIG|GPUREG_VSH_CODETRANSFER_CONFIG]]
| ?
| ?
|-
|-
| 02CC
| 02CC
| [[#GPUREG_VSH_CODE_DATA|GPUREG_VSH_CODE_DATA]]
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|
|-
|-
| 02CD
| 02CD
| [[#GPUREG_VSH_CODE_DATA|GPUREG_VSH_CODE_DATA]]
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|
|-
|-
| 02CE
| 02CE
| [[#GPUREG_VSH_CODE_DATA|GPUREG_VSH_CODE_DATA]]
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|
|-
|-
| 02CF
| 02CF
| [[#GPUREG_VSH_CODE_DATA|GPUREG_VSH_CODE_DATA]]
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|
|-
|-
| 02D0
| 02D0
| [[#GPUREG_VSH_CODE_DATA|GPUREG_VSH_CODE_DATA]]
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|
|-
|-
| 02D1
| 02D1
| [[#GPUREG_VSH_CODE_DATA|GPUREG_VSH_CODE_DATA]]
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|
|-
|-
| 02D2
| 02D2
| [[#GPUREG_VSH_CODE_DATA|GPUREG_VSH_CODE_DATA]]
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|
|-
|-
| 02D3
| 02D3
| [[#GPUREG_VSH_CODE_DATA|GPUREG_VSH_CODE_DATA]]
| [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]]
|
|
|-
|-
|}
|}
This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes.
This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15.
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 9th attribute.
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 9th attribute.
This register toggles the geometry shader unit's output registers.
This register toggles the geometry shader unit's output registers.
==== GPUREG_GSH_CODETRANSFER_END ====
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Code data transfer end signal bit.
|}
This register's value should be set to 1 in order to finalize the transfer of geometry shader code. It is unknown whether this register is used for other functions.
==== GPUREG_GSH_FLOATUNIFORM_CONFIG ====
==== GPUREG_GSH_FLOATUNIFORM_CONFIG ====
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.
==== GPUREG_GSH_CODE_CONFIG ====
==== GPUREG_GSH_CODETRANSFER_CONFIG ====
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|}
|}
This register is used to set the offset at which upcoming geometry shader code data transferred through [[#GPUREG_GSH_CODE_DATA|GPUREG_GSH_CODE_DATA]] should be written.
This register is used to set the offset at which upcoming geometry shader code data transferred through [[#GPUREG_GSH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]] should be written.
NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long.
NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long.
==== GPUREG_GSH_CODE_DATA ====
==== GPUREG_GSH_CODETRANSFER_DATA ====
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|}
|}
This register is used to transfer geometry shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader code memory bank at the offset initially set by [[#GPUREG_GSH_CODE_CONFIG|GPUREG_GSH_CODE_CONFIG]]. The offset in question is incremented after each write to this register.
This register is used to transfer geometry shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader code memory bank at the offset initially set by [[#GPUREG_GSH_CODETRANSFER_CONFIG|GPUREG_GSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.
==== GPUREG_GSH_OPDESCS_CONFIG ====
==== GPUREG_GSH_OPDESCS_CONFIG ====
|}
|}
This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for the first 8 attributes.
This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for attributes 8 through 15.
For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 9th attribute.
For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 9th attribute.
This register toggles the vertex shader units' output registers.
This register toggles the vertex shader units' output registers.
==== GPUREG_VSH_CODETRANSFER_END ====
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| Code data transfer end signal bit.
|}
This register's value should be set to 1 in order to finalize the transfer of vertex shader code. It is unknown whether this register is used for other functions.
==== GPUREG_VSH_FLOATUNIFORM_CONFIG ====
==== GPUREG_VSH_FLOATUNIFORM_CONFIG ====
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.
==== GPUREG_VSH_CODE_CONFIG ====
==== GPUREG_VSH_CODETRANSFER_CONFIG ====
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|}
|}
This register is used to set the offset at which upcoming vertex shader code data transferred through [[#GPUREG_VSH_CODE_DATA|GPUREG_VSH_CODE_DATA]] should be written.
This register is used to set the offset at which upcoming vertex shader code data transferred through [[#GPUREG_VSH_CODETRANSFER_DATA|GPUREG_VSH_CODETRANSFER_DATA]] should be written.
NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long.
NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long.
==== GPUREG_VSH_CODE_DATA ====
==== GPUREG_VSH_CODETRANSFER_DATA ====
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|}
|}
This register is used to transfer vertex shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader code memory bank at the offset initially set by [[#GPUREG_VSH_CODE_CONFIG|GPUREG_VSH_CODE_CONFIG]]. The offset in question is incremented after each write to this register.
This register is used to transfer vertex shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader code memory bank at the offset initially set by [[#GPUREG_VSH_CODETRANSFER_CONFIG|GPUREG_VSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.
==== GPUREG_VSH_OPDESCS_CONFIG ====
==== GPUREG_VSH_OPDESCS_CONFIG ====