Line 15:
Line 15:
== Aliases ==
== Aliases ==
−
It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the GPU command grouping bit which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]] so that a grouped command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
+
It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for [[GPU Commands]], which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]]
== Register list ==
== Register list ==
Line 341:
Line 341:
|-
|-
| 004F
| 004F
−
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]
+
| [[#GPUREG_VSH_OUTMAP_TOTAL|GPUREG_VSH_OUTMAP_TOTAL]]
|
|
|-
|-
| 0050
| 0050
−
| [[#GPUREG_SH_OUTMAP_O0|GPUREG_SH_OUTMAP_O0]]
+
| [[#GPUREG_VSH_OUTMAP_O0|GPUREG_VSH_OUTMAP_O0]]
|
|
|-
|-
| 0051
| 0051
−
| [[#GPUREG_SH_OUTMAP_O1|GPUREG_SH_OUTMAP_O1]]
+
| [[#GPUREG_VSH_OUTMAP_O1|GPUREG_VSH_OUTMAP_O1]]
|
|
|-
|-
| 0052
| 0052
−
| [[#GPUREG_SH_OUTMAP_O2|GPUREG_SH_OUTMAP_O2]]
+
| [[#GPUREG_VSH_OUTMAP_O2|GPUREG_VSH_OUTMAP_O2]]
|
|
|-
|-
| 0053
| 0053
−
| [[#GPUREG_SH_OUTMAP_O3|GPUREG_SH_OUTMAP_O3]]
+
| [[#GPUREG_VSH_OUTMAP_O3|GPUREG_VSH_OUTMAP_O3]]
|
|
|-
|-
| 0054
| 0054
−
| [[#GPUREG_SH_OUTMAP_O4|GPUREG_SH_OUTMAP_O4]]
+
| [[#GPUREG_VSH_OUTMAP_O4|GPUREG_VSH_OUTMAP_O4]]
|
|
|-
|-
| 0055
| 0055
−
| [[#GPUREG_SH_OUTMAP_O5|GPUREG_SH_OUTMAP_O5]]
+
| [[#GPUREG_VSH_OUTMAP_O5|GPUREG_VSH_OUTMAP_O5]]
|
|
|-
|-
| 0056
| 0056
−
| [[#GPUREG_SH_OUTMAP_O6|GPUREG_SH_OUTMAP_O6]]
+
| [[#GPUREG_VSH_OUTMAP_O6|GPUREG_VSH_OUTMAP_O6]]
|
|
|-
|-
Line 2,629:
Line 2,629:
|-
|-
| 028B
| 028B
−
| [[#GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]
+
| [[#GPUREG_028B|GPUREG_028B]]
|
|
|-
|-
| 028C
| 028C
−
| [[#GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]
+
| [[#GPUREG_028C|GPUREG_028C]]
|
|
|-
|-
| 028D
| 028D
−
| [[#GPUREG_GSH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]
+
| [[#GPUREG_028D|GPUREG_028D]]
|
|
|-
|-