Difference between revisions of "SHA Registers"
Jump to navigation
Jump to search
| Line 40: | Line 40: | ||
| 0=Hash ready, 1=Normal, 2=Final Round | | 0=Hash ready, 1=Normal, 2=Final Round | ||
|- | |- | ||
| − | |3 | + | | 3 |
| − | | Endianess (0=Little endian, 1=Big endian) | + | | Output Endianess (0=Little endian, 1=Big endian) |
|- | |- | ||
| − | |4 | + | | 4-5 |
| − | + | | Mode (0=SHA256, 0=SHA224, 2=3=SHA1) | |
| − | |||
| − | |||
| − | | Mode (0=SHA256, | ||
|- | |- | ||
| 8 | | 8 | ||
| Line 62: | Line 59: | ||
This reg contains the total size of the data written to REG_SHA_IN. | This reg contains the total size of the data written to REG_SHA_IN. | ||
| − | == | + | == SHA_HASH == |
| − | This reg contains the SHA* hash after the final round. | + | This reg contains the SHA* hash after the final round, and the internal state during normal rounds. It is possible to write the internal state using this register. |
== SHA_IN == | == SHA_IN == | ||
The data to be hashed must be written here. The data must be padded with 0x00s to align with the register size (if needed). | The data to be hashed must be written here. The data must be padded with 0x00s to align with the register size (if needed). | ||
Revision as of 02:07, 20 March 2015
Registers
| Old3DS | Name | Address | Width | Used by |
|---|---|---|---|---|
| Yes | SHA_CNT | 0x1000A000 | 4 | Boot9, Process9 |
| Yes | SHA_INPUTSZ | 0x1000A004 | 4 | Process9 |
| Yes | SHA_OUT | 0x1000A040 | 0x20 | Process9 |
| Yes | SHA_IN | 0x1000A080 | 0x40 | Boot9, Process9 |
SHA_CNT
| Bits | Description |
|---|---|
| 0-1 | 0=Hash ready, 1=Normal, 2=Final Round |
| 3 | Output Endianess (0=Little endian, 1=Big endian) |
| 4-5 | Mode (0=SHA256, 0=SHA224, 2=3=SHA1) |
| 8 | Unknown. When set, the *entire* ARM9 hangs/crashes when attempting to read REG_SHA_IN. |
| 24 | Enable |
| 25 | 1 when FIFO expects read/write |
SHA_INPUTSZ
This reg contains the total size of the data written to REG_SHA_IN.
SHA_HASH
This reg contains the SHA* hash after the final round, and the internal state during normal rounds. It is possible to write the internal state using this register.
SHA_IN
The data to be hashed must be written here. The data must be padded with 0x00s to align with the register size (if needed).