These registers are responsible for controlling how framebuffer data can be DMA'd from the DS GPU, and also for configuring the upscaling matrix.
Registers
The physical address can be calculated by subtracting 0xEB00000 from the virtual address.
Control
| VAddress
|
Name
|
Width
|
| 0x1EC1x000
|
MTX_CNT
|
4
|
| 0x1EC1x004
|
MTX_SIZE
|
4
|
| 0x1EC1x008
|
MTX_ACK
|
4
|
| 0x1EC1x00C
|
???
|
4
|
| 0x1EC1x020
|
???
|
4
|
Matrix unit
There are two matrix units, one at +0x200, and the other one at +0x300, possibly one for each axis (X and Y)
| VAddress
|
Name
|
Width
|
Description
|
| 0x1EC1xn00
|
KRN_WIDTH
|
4
|
Kernel width - 1 is written here, 1 <= width <= 8
This decides how many pixels are written each batch.
|
| 0x1EC1xn04
|
KRN_PATTERN_BITS
|
4
|
If the corresponding bit for the current batch iteration index is set then a new pixel is read.
The amount of set bits determine how many pixels are read each batch. Any bit indexes past KRN_WIDTH are ignored.
This value is 8 bits, but it has to be written with a 32bit write.
|
| 0x1EC1xn40
|
KRN_MTX
|
0xC0
|
int kerneldata[6][8]; - matrix data is written here, height is always 6
|
Descriptions
MTX_CNT
| Bit(s)
|
Description
|
| 0
|
Enable bit
|
| 1
|
??? set after init sequence
|
| 2
|
??? set after init sequence
|
| 3
|
???
|
| 4
|
???
|
| 8-9
|
Input pixel mode? 0 = 4byte color, 1 = 3byte color, 2 = 2byte color, 3 = 2byte color
|
| 10-11
|
Output pixel mode? Same enum as above.
|
| 12
|
??? initialized to 0, but if set then requires the output width and height to be multiples of 8
|
| 15
|
??? set after init sequence
|
| 16
|
??? not yet inited bit ???
|
MTX_SIZE
| Bit(s)
|
Description
|
| 0-8
|
Output framebuffer width - 1 is written here
|
| 16-25
|
Output framebuffer height - 1 is written here
|
MTX_ACK
Reading this register will return pending interrupts.
Writing this register will acknowledge the pending interrupt.
| Bit(s)
|
Description
|
| 0
|
Interrupt 0
|
| 1
|
Interrupt 1
|
| 2
|
Interrupt 2
|