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CONFIG9 Registers (edit)

Revision as of 19:56, 27 September 2014

307 bytes removed ,  19:56, 27 September 2014
no edit summary
Line 5: Line 5:  
!  WIDTH
 
!  WIDTH
 
|-
 
|-
−
| ?
+
| REG_SYSPROT9
 
| 0x10000000
 
| 0x10000000
 
| 1
 
| 1
 
|-
 
|-
−
| ?
+
| REG_SYSPROT11
 
| 0x10000001
 
| 0x10000001
 
| 1
 
| 1
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| 2
 
| 2
 
|-
 
|-
−
| ?
+
| REG_CARDCTRL
 
| 0x10000010
 
| 0x10000010
 
| 1
 
| 1
 
|-
 
|-
 
| ?
 
| ?
−
| 0x10000200
+
| 0x10000011
 
| 1
 
| 1
 +
|-
 +
| ?
 +
| 0x10000012
 +
| 2
 +
|-
 +
| ?
 +
| 0x10000204
 +
| 2
 
|-
 
|-
 
| ?
 
| ?
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* Selecting CTRCARD2 will activate the register space at [[CTRCARD|0x10005000]].
 
* Selecting CTRCARD2 will activate the register space at [[CTRCARD|0x10005000]].
   −
== 0x10000000, Hidden bootrom off-switch ==  
+
== REG_SYSPROT9 ==  
−
The ARM9 and ARM11 [[Memory_layout|bootroms]](+0x8000) are disabled by writing 1 to (u8*)0x10000000 and 1 to (u8*)0x10000001?(These two registers are written by the ARM9)
+
 
 +
Writing values to SYSPROT sets the specified bitmask. The ARM9 [[Memory_layout|bootrom]](+0x8000) is disabled by writing bit0. bit1 is used by NATIVE_FIRM to make sure console-unique TWL AES-keys are only set at hard-boot. It is not possible to set any other bits.
   −
Writing values here(u8 0x10000000+0) sets the specified bitmask. Thus, writing value 0x2 when the register(u8 0x10000000+0) was previously set to value 0x1 changes the value to 0x3. During the NATIVE_FIRM ARM9 kernel startup, it will check if bitmask 0x2 in this register is set. If that bitmask is not set, the console-unique portions of the two console-unique TWL [[AES|keyslots]] are then initialized. The kernel then writes value 0x2 to this register, regardless of the previous bitmask value(due to this, the console-unique TWL key-data init is only done at hard-boot).
+
== REG_SYSPROT11 ==
 +
ARM11 bootrom (+0x8000) is disabled by writing bit0. It is not possible to set any other bits.
    
== 0x10010000 ==
 
== 0x10010000 ==
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