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CSND Registers (edit)

Revision as of 13:07, 29 June 2014

640 bytes added ,  13:07, 29 June 2014
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=0x1EC03000=
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{| class="wikitable" border="1"
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!  NAME
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!  PHYSICAL ADDRESS
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!  WIDTH
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!  DESCRIPTION
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|-
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| REG_DSP_FIFO
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| 0x1ED03000
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| 2
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|
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|-
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| REG_DSP_??
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| 0x1ED03004
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| 2
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| ???
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|-
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| REG_DSP_FIFO_CNT
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| 0x1ED03008
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| 2
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|
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|-
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| REG_DSP_??
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| 0x1ED03010
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| 2
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| ???
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|-
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| REG_DSP_STATUS
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| 0x1ED0300C
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| 2
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|
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|-
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| REG_DSP_??
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| 0x1ED03014
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| 2
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| ???
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|-
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| REG_DSP_??
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| 0x1ED03018
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| 2
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| ???
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|-
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| REG_DSP_??
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| 0x1ED0301C
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| 2
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| ???
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|-
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| REG_DSP_PORT<0-2>
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| 0x1ED03020
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| 3*8=0x18
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|
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|}
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=== REG_DSP_STATUS ===
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bit1,8: FIFO WRITE ERRORS?
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bit6: FIFO_READ_READY
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bit7: FIFO_WRITE_READY
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bit9: ???
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bit10-12: PORT<0-2>_RECV_READY
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bit13-15: PORT<0-2>_SEND_READY
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 +
 
=0x1EC03400=
 
=0x1EC03400=
 
The channel registers are based at 0x1EC03400(process virtual address). There's 0x20-bytes total for each channel slot, thus the base-address for a channel's slot is determined with: 0x1EC03400 + (channel_index*0x20). The below offsets are relative to these channel register slots.
 
The channel registers are based at 0x1EC03400(process virtual address). There's 0x20-bytes total for each channel slot, thus the base-address for a channel's slot is determined with: 0x1EC03400 + (channel_index*0x20). The below offsets are relative to these channel register slots.
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