Changes

210 bytes added ,  21:28, 6 November 2012
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=Description=
 
=Description=
This loads a [[CRR0|CRR]] for the RO module, only one CRR can be loaded at a time.
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This loads a [[CRR0|CRR]] for the RO module, only one CRR can be loaded at a time. Before RO verifies the input CRR, RO uses [[SVC|ControlProcessMemory]] to set the memory permissions of the input buffer in the process to R--. If verification of the CRR fails, the permissions are set to RW-.