− | This loads a [[CRR0|CRR]] for the RO module, only one CRR can be loaded at a time. | + | This loads a [[CRR0|CRR]] for the RO module, only one CRR can be loaded at a time. Before RO verifies the input CRR, RO uses [[SVC|ControlProcessMemory]] to set the memory permissions of the input buffer in the process to R--. If verification of the CRR fails, the permissions are set to RW-. |