Changes

|-

|-

| style="background: green" | Yes

| style="background: green" | Yes

| [[#LGY_SLEEP|LGY_SLEEP]]

| [[#LGY_SLEEP_CNT|LGY_SLEEP_CNT]]

| 0x10141104

| 0x10141104

| 2

| 2

|-

|-

| style="background: green" | Yes

| style="background: green" | Yes

| [[#LGY_PADCNT|LGY_PADCNT]]

| [[#LGY_PAD_CNT|LGY_PAD_CNT]]

| 0x1014110A

| 0x1014110A

| 2

| 2

|-

|-

| 1

| 1

| [[HID_Registers#HID_PADCNT|HID_PADCNT]]

| [[HID_Registers#HID_PAD_CNT|HID_PAD_CNT]]

|-

|-

| 3

| 3

The very last 3DS-mode register poke the [[FIRM|TWL_FIRM]] Process9 does before it gets switched into TWL-mode, is writing 0x8000 to this register. Before writing this register, TWL Process9 waits for ARM7 to change the value of this register. The Process9 code for this runs from ITCM, since switching into TWL-mode includes remapping all ARM9 physical memory.

The very last 3DS-mode register poke the [[FIRM|TWL_FIRM]] Process9 does before it gets switched into TWL-mode, is writing 0x8000 to this register. Before writing this register, TWL Process9 waits for ARM7 to change the value of this register. The Process9 code for this runs from ITCM, since switching into TWL-mode includes remapping all ARM9 physical memory.

==LGY_SLEEP==

==LGY_SLEEP_CNT==

{| class="wikitable" border="1"

{| class="wikitable" border="1"

!  Bits

!  Bits

[[ARM11_Interrupts|Arm11 interrupt]] enable bits for legacy interrupts, same bit layout as the GPIOEMU regs below.

[[ARM11_Interrupts|Arm11 interrupt]] enable bits for legacy interrupts, same bit layout as the GPIOEMU regs below.

==LGY_PADCNT==

==LGY_PAD_CNT==

Also named "KEYCNT" on certain other DS(i)/GBA documentations.

Also named "KEYCNT" on certain other DS(i)/GBA documentations.

The value of this register is copied to [[HID_Registers|HID_PADCNT]] when GBA mode enters sleep.

The value of this register is copied to [[HID_Registers|HID_PAD_CNT]] when GBA mode enters sleep.

==LGY_HIDEMU_MASK==

==LGY_HIDEMU_MASK==