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PDN Registers (edit)

Revision as of 01:01, 20 January 2021

717 bytes added ,  01:01, 20 January 2021
Cleanup
Line 1: Line 1: −
= Registers =
+
=Register table=
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Old3DS
 
!  Old3DS
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| 0x10141000
 
| 0x10141000
 
| 2
 
| 2
−
| Kernel11, TwlBg
+
| Kernel11
 
|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
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| [[#PDN_VRAM_CNT|PDN_VRAM_CNT]]
 
| [[#PDN_VRAM_CNT|PDN_VRAM_CNT]]
 
| 0x10141204
 
| 0x10141204
−
| 4
+
| 1
 
| Boot11, Kernel11, TwlBg
 
| Boot11, Kernel11, TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| [[#PDN_LCD_CNT|PDN_LCD_CNT]]
 +
| 0x10141208
 +
| 1
 +
| Boot11
 
|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
Line 111: Line 117:  
|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
−
| [[#PDN_CODEC_CNT|PDN_CODEC_CNT]]
+
| [[#PDN_I2S_CNT|PDN_I2S_CNT]]
 
| 0x10141220
 
| 0x10141220
 
| 1
 
| 1
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| 1
 
| 1
 
| Process9, [[PDN Services]]
 
| Process9, [[PDN Services]]
 +
|-
 +
| style="background: red" | No
 +
| [[#PDN_MVD_CNT|PDN_MVD_CNT]]
 +
| 0x10141240
 +
| 1
 +
|
 
|-style="border-top: double"
 
|-style="border-top: double"
 
| style="background: red" | No
 
| style="background: red" | No
−
| [[#PDN_MPCORE_SOCMODE|PDN_MPCORE_SOCMODE]]
+
| [[#PDN_LGR_SOCMODE|PDN_LGR_SOCMODE]]
 
| 0x10141300
 
| 0x10141300
 
| 2
 
| 2
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|-
 
|-
 
| style="background: red" | No
 
| style="background: red" | No
−
| [[#PDN_MPCORE_CNT|PDN_MPCORE_CNT]]
+
| [[#PDN_LGR_CNT|PDN_LGR_CNT]]
 
| 0x10141304
 
| 0x10141304
 
| 2
 
| 2
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|-
 
|-
 
| style="background: red" | No
 
| style="background: red" | No
−
| [[#PDN_MPCORE_BOOTCNT<0-3>|PDN_MPCORE_BOOTCNT]]<0-3>
+
| [[#PDN_LGR_CPU_CNT<0-3>|PDN_LGR_CPU_CNT]]<0-3>
 
| 0x10141310
 
| 0x10141310
 
| 1*4
 
| 1*4
Line 147: Line 159:  
|}
 
|}
    +
=Sleep registers=
 
==PDN_CNT==
 
==PDN_CNT==
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
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|-
 
|-
 
| 15
 
| 15
−
| 1 = VRAM is in self-refresh mode
+
| 1 = VRAM is powered down
 
|}
 
|}
   −
Kernel11 puts VRAM in self-refresh mode (before going to sleep) by first disabling the 8 banks using [[GPU/External_Registers#Map|GX register 0x10400030]], then by disabling the GPU clock using [[#PDN_GPU_CNT|PDN_GPU_CNT]] bit 16 and finally polls this register.
+
Kernel11 powers down VRAM (it's unclear whether bit15 is power-down or self-refresh mode) by first disabling the 8 banks using [[GPU/External_Registers#Map|GX register 0x10400030]], then by disabling the GPU clock using [[#PDN_GPU_CNT|PDN_GPU_CNT]] bit 16 and finally writes to and polls this register.
    
==PDN_WAKE_ENABLE==
 
==PDN_WAKE_ENABLE==
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For each bit, write 1 to acknowledge, and 0 to clear (?).
 
For each bit, write 1 to acknowledge, and 0 to clear (?).
   −
==PDN_WIFICNT==
+
=Legacy registers=
−
{| class="wikitable" border="1"
  −
!  Old3DS
  −
!  Bits
  −
!  Description
  −
|-
  −
| style="background: green" | Yes
  −
| 0
  −
| Enable wifi subsystem
  −
|}
  −
 
   
==LGY_MODE==
 
==LGY_MODE==
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
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See above
 
See above
    +
=Clock and reset registers=
 
==PDN_GPU_CNT==
 
==PDN_GPU_CNT==
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
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|-
 
|-
 
| 0
 
| 0
−
| GPU External register block reset. 0 = reset.
+
| GPU main block + VRAM + LCD reset. 0 = reset.
 
|-
 
|-
 
| 1
 
| 1
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|-
 
|-
 
| 16
 
| 16
−
| Clock enable for all blocks and VRAM. 1 = enable.
+
| Clock enable for all blocks, VRAM and LCD. 1 = enable.
 
|}
 
|}
−
Bit0: main (?) nRESET (active low), unset to reset (when not on reset, external GPU registers at 0x10400000+ are enabled).
  −
When this is unset VRAM is not accessible and triggers exceptions.
      
PDN uses a 12 ARM11 cycle delay to deassert reset.
 
PDN uses a 12 ARM11 cycle delay to deassert reset.
    
==PDN_VRAM_CNT==
 
==PDN_VRAM_CNT==
−
Bit0: Enable VRAM clock in older models??
+
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Clock. 1 = enable, 0 = disable
 +
|}
 +
 
 +
This register seems to be unimplemented in released models: while it is used in tandem with PDN_GPU_CNT.bit16 in Boot11 screeninit code, Kernel11 only uses PDN_GPU_CNT.bit16 to power-off VRAM before going to sleep.
 +
 
 +
==PDN_LCD_CNT==
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Clock. 1 = enable, 0 = disable
 +
|}
   −
This register seems to be unimplemented in released models: while it is used in tandem with PDN_GPU_CNT.bit16 in boot11 screeninit code, Kernel11 only uses PDN_GPU_CNT.bit16 to put VRAM in self-refresh mode.
+
This register seems to be unimplemented in released models, only to be used in Boot11, as PDN_GPU_CNT.bit16 also drives the LCD clock.
    
==PDN_FCRAM_CNT==
 
==PDN_FCRAM_CNT==
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| Acknowledge clock request. Gets set or unset when toggling bit 1.
 
| Acknowledge clock request. Gets set or unset when toggling bit 1.
 
|}
 
|}
−
Twl-/AgbBg use this to disable FCRAM for the GBA rom in GBA mode or DSi main RAM in DSi mode. Agb-/TwlBg clears bit 0 in reg 0x10201000 before touching this reg.
+
Twl-/AgbBg use this to disable FCRAM for the GBA rom in GBA mode or DSi main RAM in DSi mode. AgbBg clears bit 0 in reg 0x10201000 before touching this reg.
 +
 
 +
Kernel11 uses it to put the FCRAM in self-refresh mode (clock disable) before going to sleep.
 +
 
 +
==PDN_I2S_CNT==
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| I2S1 Clock (maybe?) 1 = enable, 0 = disable
 +
|-
 +
| 1
 +
| I2S2 Clock. 1 = enable, 0 = disable
 +
|}
   −
Kernel11 uses it before going to sleep. It does a dummy read before touching this reg.
+
I2S1 clock enable bit seems to be unimplemented. Maybe it's because DSP clock enable drives it?
    
==PDN_CAMERA_CNT==
 
==PDN_CAMERA_CNT==
−
This is the power register used for the [[PDN_Services|PDN]] camera service.
+
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Clock. 1 = enable, 0 = disable
 +
|}
 +
 
 +
==PDN_DSP_CNT==
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Reset. 0 = reset.
 +
|-
 +
| 1
 +
| Clock. 1 = enable, 0 = disable
 +
|}
   −
bit0 = unknown, bit1 = turn on/off cameras, rest = always 0.
+
PDN services holds reset for 0x30 Arm11 cycles.
   −
==PDN_DSP_CNT==
+
==PDN_MVD_CNT==
−
This is the power register used for the [[PDN_Services|PDN Services]] DSP service.
+
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Reset. 0 = reset
 +
|}
   −
bit0: NRESET (active low). Unset to reset/hold reset.
+
This doesn't seem to be used by anything, but does have a clear effect on the hardware.
−
bit1: enable bit.
     −
PDN services holds reset for 0x30 Arm11 cycles.
+
The reset value for this register is 1 (out-of-reset at boot).
   −
== PDN_MPCORE_SOCMODE ==
+
=N3DS SoC (LGR) registers=
 +
== PDN_LGR_SOCMODE ==
 
This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read.
 
This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read.
   Line 443: Line 500:  
* 0x1F, 0x2F, 0x4F, 0x8F, 0xFF: Same result as 0x05.
 
* 0x1F, 0x2F, 0x4F, 0x8F, 0xFF: Same result as 0x05.
   −
== PDN_MPCORE_CNT ==
+
== PDN_LGR_CNT ==
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 455: Line 512:  
|}
 
|}
   −
Kernel11 sets this to 0x101 when bit 2 in [[CONFIG11 Registers#CFG11_SOCINFO|CFG11_SOCINFO]] is set otherwise 1.
+
Kernel11 sets this to 0x101 when bit 2 in [[CONFIG11 Registers#CFG11_SOCINFO|CFG11_SOCINFO]] (LGR2 supported) is set otherwise 1.
   −
== PDN_MPCORE_BOOTCNT<0-3> ==
+
== PDN_LGR_CPU_CNT<0-3> ==
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Retrieved from "https://www.3dbrew.org/wiki/Special:MobileDiff/21431...21440"