Changes

|-style="border-top: double"

|-style="border-top: double"

| style="background: red" | No

| style="background: red" | No

| [[#PDN_MPCORE_CLKCNT|PDN_MPCORE_CLKCNT]]

| [[#PDN_MPCORE_SOCMODE|PDN_MPCORE_SOCMODE]]

| 0x10141300

| 0x10141300

| 2

| 2

PDN services holds reset for 0x30 Arm11 cycles.

PDN services holds reset for 0x30 Arm11 cycles.

== PDN_MPCORE_CLKCNT ==

== PDN_MPCORE_SOCMODE ==

This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read.

This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read.

!  Description

!  Description

|-

|-

| 0

| 0-2

| Enable clock multiplier? This must be set to 1 before writing a non-zero value to bit1-2, otherwise freeze. This enables the New 3DS FCRAM extension.

| SoC mode. 0=O3DS, 1=N3DS, 5=N3DS 804MHz, 2=N3DS prototype (?), 3=N3DS prototype 536MHz (N3DS modes enable the New 3DS FCRAM extension)

|-

| Clock multiplier (0=1x, 1=2x, 2=3x, 3=hang)

|-

|-

| 15

| 15

| Busy

| Busy

|}

|}

[[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of [[CONFIG11 Registers#CFG11_SOCINFO|CFG11_SOCINFO]]:

[[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of [[CONFIG11 Registers#CFG11_SOCINFO|CFG11_SOCINFO]]: