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CONFIG11 Registers (edit)

Revision as of 15:14, 25 April 2020

902 bytes added ,  15:14, 25 April 2020
Some juicy legacy mode details.
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|-style="border-top: double"
 
|-style="border-top: double"
 
| style="background: green" | Yes
 
| style="background: green" | Yes
−
| [[#CFG11_TWLMODE_0|CFG11_TWLMODE_0]]
+
| [[#LGY_MODE|LGY_MODE]]
 
| 0x10141100
 
| 0x10141100
 
| 2
 
| 2
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|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
−
| [[#CFG11_TWLMODE_1|CFG11_TWLMODE_1]]
+
| [[#LGY_SLEEP|LGY_SLEEP]]
 
| 0x10141104
 
| 0x10141104
 
| 2
 
| 2
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|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
−
| [[#CFG11_TWLMODE_2|CFG11_TWLMODE_2]]
+
| [[#LGY_IRQ_?|LGY_IRQ_?]]
 
| 0x10141108
 
| 0x10141108
 
| 2
 
| 2
Line 152: Line 152:  
|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
−
| [[#CFG11_TWLMODE_HID|CFG11_TWLMODE_HID]]
+
| [[#LGY_PADCNT|LGY_PADCNT]]
 
| 0x1014110A
 
| 0x1014110A
 
| 2
 
| 2
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|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
−
| CFG11_GPU_FCRAM_CNT
+
| CFG11_FCRAM_CNT
 
| 0x10141210
 
| 0x10141210
 
| 2
 
| 2
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|-
 
|-
 
| 0
 
| 0
−
| Enable [[SPI Registers]] 0x10160000.
+
| Enable [[SPI Registers]] 0x10160800.
 
|-
 
|-
 
| 1
 
| 1
−
| Enable [[SPI Registers]] 0x10142000.
+
| Enable [[SPI Registers]] 0x10142800.
 
|-
 
|-
 
| 2
 
| 2
−
| Enable [[SPI Registers]] 0x10143000.
+
| Enable [[SPI Registers]] 0x10143800.
 
|}
 
|}
   Line 517: Line 517:  
|}
 
|}
   −
==CFG11_TWLMODE_0==
+
==LGY_MODE==
−
Observed 0x8001 when running under TWL_ and AGB_FIRM, 0 NATIVE_FIRM.
+
{| class="wikitable" border="1"
−
 
+
!  Bits
−
This address is poked from ARM7 to signal that it has booted and begun executing code. The ARM7-mode address for this register is 0x4700000.
+
!  Description
 +
|-
 +
| 0-1
 +
| Read only legacy mode set on reg 0x10018000.
 +
|-
 +
| 2-14
 +
| Unused.
 +
|-
 +
| 15
 +
| 1 = enable legacy mode.
 +
|}
 +
To boot into DSi or GBA mode first set register 0x10018000 to the desired mode and setup LgyFb. Then disable FCRAM by clearing bit 0 in reg 0x10201000, writing 0 to CFG11_GPU_FCRAM_CNT followed by 1 and waiting for bit 3 to clear.
    
The very last 3DS-mode register poke the [[FIRM|TWL_FIRM]] Process9 does before it gets switched into TWL-mode, is writing 0x8000 to this register. Before writing this register, TWL Process9 waits for ARM7 to change the value of this register. The Process9 code for this runs from ITCM, since switching into TWL-mode includes remapping all ARM9 physical memory.
 
The very last 3DS-mode register poke the [[FIRM|TWL_FIRM]] Process9 does before it gets switched into TWL-mode, is writing 0x8000 to this register. Before writing this register, TWL Process9 waits for ARM7 to change the value of this register. The Process9 code for this runs from ITCM, since switching into TWL-mode includes remapping all ARM9 physical memory.
   −
Writing 0x8000 to here from the ARM9 with NATIVE_FIRM running doesn't seem to do anything, other reg-pokes likely need done first.
+
==LGY_SLEEP==
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Write 1 to wakeup GBA mode.
 +
|-
 +
| 1
 +
| Sleep state/ack. 1 when GBA mode entered sleep. Write 1 to ack.
 +
|-
 +
| 2
 +
| ?
 +
|-
 +
| 3-14
 +
| Unused.
 +
|-
 +
| 15
 +
| 1 = IRQ enable (IRQ 0x59)
 +
|}
 +
When a GBA game enters sleep mode and bit 15 is 1, IRQ 0x59 fires and bit 1 is set. Bit 1 must be acknowledged/written together with bit 0 otherwise GBA mode wakes up from sleep early sometimes.
   −
==CFG11_TWLMODE_1==
+
==LGY_IRQ_?==
−
Observed 0x8000 when running under TWL_FIRM, 0 NATIVE_FIRM.
  −
 
  −
==CFG11_TWLMODE_2==
   
Bitfield.
 
Bitfield.
   −
==CFG11_TWLMODE_HID==
+
==LGY_PADCNT==
−
The value of this register is copied to [[HID_Registers|HID_?]] under certain conditions.
+
The value of this register is copied to [[HID_Registers|HID_?]] when GBA mode enters sleep.
    
==CFG11_WIFIUNK==
 
==CFG11_WIFIUNK==
Line 555: Line 583:     
==CFG11_GPU_CNT==
 
==CFG11_GPU_CNT==
−
This one seems to control the LCD/GPU/Backlight.
+
{| class="wikitable" border="1"
−
 
+
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Unknown reset. 0 = reset.
 +
|-
 +
| 1
 +
| PSC block reset? 0 = reset.
 +
|-
 +
| 2
 +
| Geoshader block reset? 0 = reset.
 +
|-
 +
| 3
 +
| Rasterization block reset? 0 = reset.
 +
|-
 +
| 4
 +
| PPF block reset. 0 = reset.
 +
|-
 +
| 5
 +
| PDC block reset? 0 = reset.
 +
|-
 +
| 6
 +
| PDC related reset. 0 = reset.
 +
|-
 +
| 7-15
 +
| Unused.
 +
|-
 +
| 16
 +
| Clock enable for all blocks. 1 = enable.
 +
|}
 
Bit0: main (?) nRESET (active low), unset to reset (when not on reset, external GPU registers at 0x10400000+ are enabled).
 
Bit0: main (?) nRESET (active low), unset to reset (when not on reset, external GPU registers at 0x10400000+ are enabled).
 
When this is unset VRAM is not accessible and triggers exceptions.
 
When this is unset VRAM is not accessible and triggers exceptions.
   −
Bits 1..6: other nRESET bits.
+
PDN uses a 12 ARM11 cycle delay to deassert reset.
−
 
  −
Bit16: Enable/Turn on LCD backlight.
  −
 
  −
PDN uses a 12 Arm11 cycle delay to deassert reset.
      
==CFG11_GPU_CNT2==
 
==CFG11_GPU_CNT2==
 
Bit0: Power on GPU?
 
Bit0: Power on GPU?
   −
==CFG11_GPU_FCRAM_CNT==
+
==CFG11_FCRAM_CNT==
−
Bit1: Enable/disable FCRAM.
+
{| class="wikitable" border="1"
−
Bit2: Enable/disable operation in progress.
+
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| Reset. 0 = reset.
 +
|-
 +
| 1
 +
| Enable something. 1 = enable.
 +
|-
 +
| 2
 +
| Acknowledge? Gets set or unset when toggling bit 1.
 +
|}
 +
Twl-/AgbBg use this to disable FCRAM for the GBA rom in GBA mode or DSi main RAM in DSi mode. Agb-/TwlBg clears bit 0 in reg 0x10201000 before touching this reg.
    
==CFG11_CODEC==
 
==CFG11_CODEC==
Profi200
137

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