Trusted
225
edits
Changes
Update MTX bits and interrupts
|-
|-
| 0x1EC1x00C
| 0x1EC1x00C
| ???
| [[#MTX_IE|MTX_IE]]
| 4
| 4
|-
|-
|-
|-
| 0
| 0
| Enable bit (?)
| Enable bit
|-
|-
| 1
| 1
|-
|-
| 15
| 15
| Interrupt enable (?)
| Start bit (setting this will eventually raise MTX interrupt 0)
|-
|-
| 16
| 16
Reading this register will return pending interrupts.
Reading this register will return pending interrupts.
Writing this register will acknowledge the pending interrupt.
Writing this register will acknowledge pending interrupts where the bits are set.
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0
| 0
| Interrupt 0
| FIFO ready (signal to start DMA)
|-
|-
| 1
| 1
| Interrupt 1
| FIFO overrun(?) (occurs if DMA is too slow)
|-
|-
| 2
| 2
| Interrupt 2
| FIFO underrun(?) (occurs on VBlank)
|-
|-
|}
|}
==MTX_IE==
Interrupt Enable for the above interrupts.