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Created page with "=Request= {{IPC/Request}} {{#vardefine:ipc_offset|0}} {{IPC/RequestEntry|Header code [0x00040080]}} {{IPC/RequestEntry|GPU address based at 0x1EB00000, must be word-aligne..."
=Request=
{{IPC/Request}}
{{#vardefine:ipc_offset|0}}
{{IPC/RequestEntry|Header code [0x00040080]}}
{{IPC/RequestEntry|[[GPU]] address based at 0x1EB00000, must be word-aligned}}
{{IPC/RequestEntry|1 = Size, must be <=0x80 and word-aligned}}
{{IPC/RequestEnd}}
The following is located 0x100-bytes after the beginning of the above command buffer:
{{IPC/Request}}
{{#vardefine:ipc_offset|0}}
{{IPC/RequestEntry|Header code [0x00040080]}}
{{IPC/TranslateStaticBuffer|Output buffer address|0}}
{{IPC/RequestEnd}}
=Response=
{{IPC/Request}}
{{#vardefine:ipc_offset|0}}
{{IPC/RequestEntry|Header code}}
{{IPC/RequestEntry|Result code}}
{{IPC/TranslateStaticBuffer|Output data pointer|0}}
{{IPC/RequestEnd}}
=Description=
The GPU register offset must be <0x420000.
{{IPC/Request}}
{{#vardefine:ipc_offset|0}}
{{IPC/RequestEntry|Header code [0x00040080]}}
{{IPC/RequestEntry|[[GPU]] address based at 0x1EB00000, must be word-aligned}}
{{IPC/RequestEntry|1 = Size, must be <=0x80 and word-aligned}}
{{IPC/RequestEnd}}
The following is located 0x100-bytes after the beginning of the above command buffer:
{{IPC/Request}}
{{#vardefine:ipc_offset|0}}
{{IPC/RequestEntry|Header code [0x00040080]}}
{{IPC/TranslateStaticBuffer|Output buffer address|0}}
{{IPC/RequestEnd}}
=Response=
{{IPC/Request}}
{{#vardefine:ipc_offset|0}}
{{IPC/RequestEntry|Header code}}
{{IPC/RequestEntry|Result code}}
{{IPC/TranslateStaticBuffer|Output data pointer|0}}
{{IPC/RequestEnd}}
=Description=
The GPU register offset must be <0x420000.