6,264
edits
Changes
→PDN_MPCORE_CLKCNT
! Description
! Description
|-
|-
| 0x1
| 0x01
| No
| No
| Yes
| Yes
| 0x1
| 0x01
| 1x
| 1x
| 268MHz
| 268MHz
|-
|-
| 0x2
| 0x02
| No
| No
| No
| No
| 0x1
| 0x01
| 1x
| 1x
| 268MHz
| 268MHz
|-
|-
| 0x5
| 0x05
| Yes
| Yes
| Yes
| Yes
| 0x3
| 0x03
| 3x
| 3x
| 804MHz
| 804MHz
|-
|-
| 0x3
| 0x03
| Yes
| Yes
| No
| No
| 0x2
| 0x02
| 2x
| 2x
| 536MHz (tested on New3DS)
| 536MHz (tested on New3DS)
Note that the above PDN_MPCORE_CFG bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code).
Note that the above PDN_MPCORE_CFG bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code).
The following other register value(s) were tested on New3DS, which are not used by the kernel:
The following register value(s) were tested on New3DS by patching the kernel:
* 0x0: Entire system hangs.
* 0x2: Entire system hangs.
* 0x3: ARM11 runs at 536MHz.
* 0x4: Entire system hangs.
* 0x4: Entire system hangs.
* 0x6: Entire system hangs.
* 0x6: Entire system hangs.
* 0xD: Same result as 0x05.
== PDN_MPCORE_CNT ==
== PDN_MPCORE_CNT ==