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mLine 3,998:
Line 3,998: − === Geometry pipeline registers ===+ − ==== GPUREG_GEOSTAGE_CONFIG ====+ Line 4,021:
Line 4,021: − === Geometry shader registers ===+ − ==== GPUREG_GSH_BOOLUNIFORM ====+ Line 4,083:
Line 4,083: − ==== GPUREG_GSH_INTUNIFORM_I0 ====+ Line 4,104:
Line 4,104: − ==== GPUREG_GSH_INTUNIFORM_I1 ====+ Line 4,125:
Line 4,125: − ==== GPUREG_GSH_INTUNIFORM_I2 ====+ Line 4,146:
Line 4,146: − ==== GPUREG_GSH_INTUNIFORM_I3 ====+ Line 4,167:
Line 4,167: − ==== GPUREG_GSH_INPUTBUFFER_CONFIG ====+ Line 4,186:
Line 4,186: − ==== GPUREG_GSH_ENTRYPOINT ====+ Line 4,201:
Line 4,201: − ==== GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW ====+ Line 4,235:
Line 4,235: − ==== GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH ====+ Line 4,269:
Line 4,269: − ==== GPUREG_GSH_OUTMAP_MASK ====+ Line 4,299:
Line 4,299: − ==== GPUREG_GSH_CODETRANSFER_END ====+ Line 4,311:
Line 4,311: − ==== GPUREG_GSH_FLOATUNIFORM_CONFIG ====+ Line 4,326:
Line 4,326: − ==== GPUREG_GSH_FLOATUNIFORM_DATA ====+ Line 4,344:
Line 4,344: − ==== GPUREG_GSH_CODETRANSFER_CONFIG ====+ Line 4,358:
Line 4,358: − ==== GPUREG_GSH_CODETRANSFER_DATA ====+ Line 4,370:
Line 4,370: − ==== GPUREG_GSH_OPDESCS_CONFIG ====+ Line 4,382:
Line 4,382: − ==== GPUREG_GSH_OPDESCS_DATA ====+ Line 4,394:
Line 4,394: − === Vertex shader registers ===+ − ==== GPUREG_VSH_BOOLUNIFORM ====+ Line 4,456:
Line 4,456: − ==== GPUREG_VSH_INTUNIFORM_I0 ====+ Line 4,477:
Line 4,477: − ==== GPUREG_VSH_INTUNIFORM_I1 ====+ Line 4,498:
Line 4,498: − ==== GPUREG_VSH_INTUNIFORM_I2 ====+ Line 4,519:
Line 4,519: − ==== GPUREG_VSH_INTUNIFORM_I3 ====+ Line 4,540:
Line 4,540: − ==== GPUREG_VSH_INPUTBUFFER_CONFIG ====+ Line 4,558:
Line 4,558: − ==== GPUREG_VSH_ENTRYPOINT ====+ Line 4,573:
Line 4,573: − ==== GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW ====+ Line 4,607:
Line 4,607: − ==== GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH ====+ Line 4,641:
Line 4,641: − ==== GPUREG_VSH_OUTMAP_MASK ====+ Line 4,698:
Line 4,698: − ==== GPUREG_VSH_CODETRANSFER_END ====+ Line 4,710:
Line 4,710: − ==== GPUREG_VSH_FLOATUNIFORM_CONFIG ====+ Line 4,725:
Line 4,725: − ==== GPUREG_VSH_FLOATUNIFORM_DATA ====+ Line 4,743:
Line 4,743: − ==== GPUREG_VSH_CODETRANSFER_CONFIG ====+ Line 4,757:
Line 4,757: − ==== GPUREG_VSH_CODETRANSFER_DATA ====+ Line 4,769:
Line 4,769: − ==== GPUREG_VSH_OPDESCS_CONFIG ====+ Line 4,781:
Line 4,781: − ==== GPUREG_VSH_OPDESCS_DATA ====+
Move most headings up a level
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== Geometry pipeline registers ==
=== GPUREG_GEOSTAGE_CONFIG ===
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This register configures the geometry stage of the GPU pipeline.
This register configures the geometry stage of the GPU pipeline.
== Geometry shader registers ==
=== GPUREG_GSH_BOOLUNIFORM ===
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This register is used to set the geometry shader unit's boolean registers.
This register is used to set the geometry shader unit's boolean registers.
=== GPUREG_GSH_INTUNIFORM_I0 ===
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This register is used to set the geometry shader's i0 integer register.
This register is used to set the geometry shader's i0 integer register.
=== GPUREG_GSH_INTUNIFORM_I1 ===
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This register is used to set the geometry shader's i1 integer register.
This register is used to set the geometry shader's i1 integer register.
=== GPUREG_GSH_INTUNIFORM_I2 ===
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This register is used to set the geometry shader's i2 integer register.
This register is used to set the geometry shader's i2 integer register.
=== GPUREG_GSH_INTUNIFORM_I3 ===
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This register is used to set the geometry shader's i3 integer register.
This register is used to set the geometry shader's i3 integer register.
=== GPUREG_GSH_INPUTBUFFER_CONFIG ===
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=== GPUREG_GSH_ENTRYPOINT ===
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This sets the entrypoint for the program running on the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entrypoint, it can also be used to set this single shader unit to run from a different entrypoint than the other three even when running a vertex shader.
This sets the entrypoint for the program running on the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entrypoint, it can also be used to set this single shader unit to run from a different entrypoint than the other three even when running a vertex shader.
=== GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW ===
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For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 1st attribute.
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 1st attribute.
=== GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH ===
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For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 9th attribute.
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 9th attribute.
=== GPUREG_GSH_OUTMAP_MASK ===
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This register toggles the geometry shader unit's output registers.
This register toggles the geometry shader unit's output registers.
=== GPUREG_GSH_CODETRANSFER_END ===
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This register's value should be set to 1 in order to finalize the transfer of geometry shader code. It is unknown whether this register is used for other functions.
This register's value should be set to 1 in order to finalize the transfer of geometry shader code. It is unknown whether this register is used for other functions.
=== GPUREG_GSH_FLOATUNIFORM_CONFIG ===
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This register sets the target float vec4 geometry shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.
This register sets the target float vec4 geometry shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.
=== GPUREG_GSH_FLOATUNIFORM_DATA ===
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* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.
=== GPUREG_GSH_CODETRANSFER_CONFIG ===
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NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.
NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.
=== GPUREG_GSH_CODETRANSFER_DATA ===
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This register is used to transfer geometry shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader code memory bank at the offset initially set by [[#GPUREG_GSH_CODETRANSFER_CONFIG|GPUREG_GSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.
This register is used to transfer geometry shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader code memory bank at the offset initially set by [[#GPUREG_GSH_CODETRANSFER_CONFIG|GPUREG_GSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.
=== GPUREG_GSH_OPDESCS_CONFIG ===
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This register is used to set the offset at which upcoming geometry shader operand descriptor data transferred through [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]] should be written.
This register is used to set the offset at which upcoming geometry shader operand descriptor data transferred through [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]] should be written.
=== GPUREG_GSH_OPDESCS_DATA ===
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This register is used to transfer geometry shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader operand descriptor memory bank at the offset initially set by [[#GPUREG_GSH_OPDESCS_CONFIG|GPUREG_GSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.
This register is used to transfer geometry shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader operand descriptor memory bank at the offset initially set by [[#GPUREG_GSH_OPDESCS_CONFIG|GPUREG_GSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.
== Vertex shader registers ==
=== GPUREG_VSH_BOOLUNIFORM ===
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This register is used to set the vertex shader unit's boolean registers.
This register is used to set the vertex shader unit's boolean registers.
=== GPUREG_VSH_INTUNIFORM_I0 ===
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This register is used to set the vertex shader's i0 integer register.
This register is used to set the vertex shader's i0 integer register.
=== GPUREG_VSH_INTUNIFORM_I1 ===
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This register is used to set the vertex shader's i1 integer register.
This register is used to set the vertex shader's i1 integer register.
=== GPUREG_VSH_INTUNIFORM_I2 ===
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This register is used to set the vertex shader's i2 integer register.
This register is used to set the vertex shader's i2 integer register.
=== GPUREG_VSH_INTUNIFORM_I3 ===
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This register is used to set the vertex shader's i3 integer register.
This register is used to set the vertex shader's i3 integer register.
=== GPUREG_VSH_INPUTBUFFER_CONFIG ===
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This register is used to configure the vertex shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the number of attributes per vertex.
This register is used to configure the vertex shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the number of attributes per vertex.
=== GPUREG_VSH_ENTRYPOINT ===
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This sets the entrypoint for the program running on shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.
This sets the entrypoint for the program running on shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.
=== GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW ===
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For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 1st attribute.
For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 1st attribute.
=== GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH ===
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For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 9th attribute.
For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 9th attribute.
=== GPUREG_VSH_OUTMAP_MASK ===
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This register toggles the vertex shader units' output registers.
This register toggles the vertex shader units' output registers.
=== GPUREG_VSH_CODETRANSFER_END ===
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This register's value should be set to 1 in order to finalize the transfer of vertex shader code. It is unknown whether this register is used for other functions.
This register's value should be set to 1 in order to finalize the transfer of vertex shader code. It is unknown whether this register is used for other functions.
=== GPUREG_VSH_FLOATUNIFORM_CONFIG ===
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This register sets the target float vec4 vertex shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.
This register sets the target float vec4 vertex shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.
=== GPUREG_VSH_FLOATUNIFORM_DATA ===
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* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.
=== GPUREG_VSH_CODETRANSFER_CONFIG ===
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NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.
NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The [[Shader_Instruction_Set#Instruction_formats|shader control flow instructions]] only have room to address 12 bits though, so it's likely that the maximum is 4095.
=== GPUREG_VSH_CODETRANSFER_DATA ===
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This register is used to transfer vertex shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader code memory bank at the offset initially set by [[#GPUREG_VSH_CODETRANSFER_CONFIG|GPUREG_VSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.
This register is used to transfer vertex shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader code memory bank at the offset initially set by [[#GPUREG_VSH_CODETRANSFER_CONFIG|GPUREG_VSH_CODETRANSFER_CONFIG]]. The offset in question is incremented after each write to this register.
=== GPUREG_VSH_OPDESCS_CONFIG ===
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This register is used to set the offset at which upcoming vertex shader operand descriptor data transferred through [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]] should be written.
This register is used to set the offset at which upcoming vertex shader operand descriptor data transferred through [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]] should be written.
=== GPUREG_VSH_OPDESCS_DATA ===
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