Changes

| 0=Hash ready, 1=Normal, 2=Final Round

| 0=Hash ready, 1=Normal, 2=Final Round

|-

|-

|3

| 3

| Endianess (0=Little endian, 1=Big endian)

| Output Endianess (0=Little endian, 1=Big endian)

|-

|-

|4

| 4-5

| Mode (0=SHA256, 0=SHA224, 2=3=SHA1)

|-

| 5

| Mode (0=SHA256, 1=SHA1)

|-

|-

| 8

| 8

This reg contains the total size of the data written to REG_SHA_IN.

This reg contains the total size of the data written to REG_SHA_IN.

== SHA_OUT ==

== SHA_HASH ==

This reg contains the SHA* hash after the final round.

This reg contains the SHA* hash after the final round, and the internal state during normal rounds. It is possible to write the internal state using this register.

== SHA_IN ==

== SHA_IN ==

The data to be hashed must be written here. The data must be padded with 0x00s to align with the register size (if needed).

The data to be hashed must be written here. The data must be padded with 0x00s to align with the register size (if needed).