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NDMA Registers (edit)

Revision as of 22:40, 19 March 2015

518 bytes added ,  22:40, 19 March 2015
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== Registers ==
 
== Registers ==
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
−
!  NAME
+
!  Old3DS
−
!  ADDRESS
+
!  Name
−
!  WIDTH
+
!  Address
 +
!  Width
 +
!  Used by
 
|-
 
|-
−
|  REG_NDMAGCNT
+
| style="background: green" | Yes
 +
|  [[#NDMA_GLOBAL_CNT|NDMA_GLOBAL_CNT]]
 
|  0x10002000
 
|  0x10002000
 
|  4
 
|  4
 +
|
 
|-
 
|-
−
|  REG_NDMASAD(n)
+
| style="background: green" | Yes
 +
|  [[#NDMA_SRC_ADDR|NDMA_SRC_ADDR]](n)
 
|  0x10002004 + (n*0x1c)
 
|  0x10002004 + (n*0x1c)
 
|  4
 
|  4
 +
|
 
|-
 
|-
−
|  REG_NDMADAD(n)
+
| style="background: green" | Yes
 +
|  [[#NDMA_DST_ADDR|NDMA_DST_ADDR]](n)
 
|  0x10002008 + (n*0x1c)
 
|  0x10002008 + (n*0x1c)
 
|  4
 
|  4
 +
|
 
|-
 
|-
−
|  REG_NDMATCNT(n)
+
| style="background: green" | Yes
 +
|  [[#NDMA_TRANSFER_CNT|NDMA_TRANSFER_CNT]](n)
 
|  0x1000200c + (n*0x1c)
 
|  0x1000200c + (n*0x1c)
 
|  4
 
|  4
 +
|
 
|-
 
|-
−
|  REG_NDMAWCNT(n)
+
| style="background: green" | Yes
 +
|  [[#NDMA_WRITE_CNT|NDMA_WRITE_CNT]](n)
 
|  0x10002010 + (n*0x1c)
 
|  0x10002010 + (n*0x1c)
 
|  4
 
|  4
 +
|
 
|-
 
|-
−
|  REG_NDMABCNT(n)
+
| style="background: green" | Yes
 +
|  [[#NDMA_BLOCK_CNT|NDMA_BLOCK_CNT]](n)
 
|  0x10002014 + (n*0x1c)
 
|  0x10002014 + (n*0x1c)
 
|  4
 
|  4
 +
|
 
|-
 
|-
−
|  REG_NDMAFDATA(n)
+
| style="background: green" | Yes
 +
|  [[#NDMA_FILL_DATA|NDMA_FILL_DATA]](n)
 
|  0x10002018 + (n*0x1c)
 
|  0x10002018 + (n*0x1c)
 
|  4
 
|  4
 +
|
 
|-
 
|-
−
|  REG_NDMACNT(n)
+
| style="background: green" | Yes
 +
|  [[#NDMA_CNT|NDMA_CNT]](n)
 
|  0x1000201C + (n*0x1c)
 
|  0x1000201C + (n*0x1c)
 
|  4
 
|  4
 +
|
 
|}
 
|}
   −
== REG_NDMAGCNT ==
+
== NDMA_GLOBAL_CNT ==
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  BIT
 
!  BIT
Line 52: Line 70:  
|}
 
|}
   −
== REG_NDMASAD ==
+
== NDMA_SRC_ADDR ==
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  BIT
 
!  BIT
Line 60: Line 78:  
|  Source data address. Must be multiple of 4.
 
|  Source data address. Must be multiple of 4.
 
|}
 
|}
−
Like old DMA, REG_NDMASAD is copied to internal registers when written to.
+
Like old DMA, NDMA_SRC_ADDR is copied to internal registers when written to.
   −
== REG_NDMADAD ==
+
== NDMA_DST_ADDR ==
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  BIT
 
!  BIT
Line 70: Line 88:  
|  Destination data address. Must be multiple of 4.
 
|  Destination data address. Must be multiple of 4.
 
|}
 
|}
−
Like old DMA, REG_NDMADAD is copied to internal registers when written to.
+
Like old DMA, NDMA_DST_ADDR is copied to internal registers when written to.
   −
== REG_NDMATCNT ==
+
== NDMA_TRANSFER_CNT ==
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  BIT
 
!  BIT
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|}
 
|}
   −
== REG_NDMAWCNT ==
+
== NDMA_WRITE_CNT ==
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  BIT
 
!  BIT
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|}
 
|}
   −
== REG_NDMABCNT ==
+
== NDMA_BLOCK_CNT ==
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  BIT
 
!  BIT
Line 102: Line 120:  
|}
 
|}
   −
== REG_NDMAFDATA ==
+
== NDMA_FILL_DATA ==
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  BIT
 
!  BIT
Line 111: Line 129:  
|}
 
|}
   −
== REG_NDMACNT ==
+
== NDMA_CNT ==
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  BIT
 
!  BIT
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== Block transfers ==
 
== Block transfers ==
−
First, a word is always 32 bits. Second, the block transfer specified in REG_NDMACNT is the smallest atom of data that will be transferred in a burst. The bus is monopolized until this block is transferred, without splitting up.
+
First, a word is always 32 bits. Second, the block transfer specified in NDMA_CNT is the smallest atom of data that will be transferred in a burst. The bus is monopolized until this block is transferred, without splitting up.
   −
The next block transfer will happen after the specified time in the REG_NDMABCNT interval timer, until done.
+
The next block transfer will happen after the specified time in the NDMA_BLOCK_CNT interval timer, until done.
    
== Immediate mode ==
 
== Immediate mode ==
−
Transfers the words specified in REG_NDMAWCNT immediately following block transfer rules. REG_NDMATCNT and repeating mode are ignored.
+
Transfers the words specified in NDMA_WRITE_CNT immediately following block transfer rules. NDMA_TRANSFER_CNT and repeating mode are ignored.
    
== Repeating mode ==
 
== Repeating mode ==
−
Transfers the words specified in REG_NDMAWCNT following the startup mode event. REG_DMATCNT is ignored.
+
Transfers the words specified in NDMA_WRITE_CNT following the startup mode event. NDMA_TRANSFER_CNT is ignored.
    
== No immediate and no repeating mode ==
 
== No immediate and no repeating mode ==
−
Transfers the words specified in REG_NDMAWCNT for each startup event, and gets disabled when the total number of words in REG_NDMATCNT are transferred.
+
Transfers the words specified in NDMA_WRITE_CNT for each startup event, and gets disabled when the total number of words in NDMA_TRANSFER_CNT are transferred.
Retrieved from "https://www.3dbrew.org/wiki/Special:MobileDiff/11962"