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Basic implementations of the following specification can be found at [https://github.com/smealum/aemstro] and [https://github.com/neobrain/nihstro]
 
Basic implementations of the following specification can be found at [https://github.com/smealum/aemstro] and [https://github.com/neobrain/nihstro]
 
Please note that this page is being written as the instruction set is reverse engineered; as such it may very well contain mistakes.
 
Please note that this page is being written as the instruction set is reverse engineered; as such it may very well contain mistakes.
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Nomenclature :
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- opcode names with I appended to them are the same as their non-I version, except they use the inverted instruction format, giving 7 bits to SRC2 (and access to uniforms) and 5 bits to SRC1
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- opcode names with U appended to them are the same as their non-U version, except they are executed conditionally based on the value of a uniform boolean.
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- opcode names with C appended to them are the same as their non-C version, except they are executed conditionally based on a logical expression specified in the instruction.
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== Instruction formats ==
 
== Instruction formats ==
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