373
edits
Changes
fixed MAD SRC order
| 0x5
| 0x5
| 0x5
| 0x5
| Source 1 register (SRC1)
| Source 3 register (SRC3)
|-
|-
| 0xA
| 0xA
| 0x11
| 0x11
| 0x7
| 0x7
| Source 3 register (SRC3)
| Source 1 register (SRC1)
|-
|-
| 0x18
| 0x18
| 5
| 5
| MAD
| MAD
| Multiplies two vectors and adds a third one component by component; DST[i] = SRC1[i] + SRC2[i].SRC3[i] for all i (modulo destination component masking)
| Multiplies two vectors and adds a third one component by component; DST[i] = SRC3[i] + SRC2[i].SRC1[i] for all i (modulo destination component masking)
|}
|}