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GPU/Shader Instruction Set (edit)

Revision as of 22:45, 16 November 2014

366 bytes added ,  22:45, 16 November 2014
added MAD format
Line 134: Line 134:  
|  0x1A
 
|  0x1A
 
|  0x6
 
|  0x6
 +
|  Opcode
 +
|}
 +
 +
Format 5 : (used for MAD)
 +
{| class="wikitable" border="1"
 +
|-
 +
!  Offset
 +
!  Size (bits)
 +
!  Description
 +
|-
 +
|  0x0
 +
|  0x5
 +
|  Operand descriptor ID (DESC)
 +
|-
 +
|  0x5
 +
|  0x5
 +
|  Source 2 register (SRC2)
 +
|-
 +
|  0xA
 +
|  0x7
 +
|  Source 1 register (SRC1)
 +
|-
 +
|  0x11
 +
|  0x7
 +
|  Source 3 register (SRC3)
 +
|-
 +
|  0x18
 +
|  0x5
 +
|  Destination register (DST)
 +
|-
 +
|  0x1D
 +
|  0x3
 
|  Opcode
 
|  Opcode
 
|}
 
|}
Smea
373

edits

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