GPU/Shader Instruction Set
< GPU
Overview
Instructions are coded in little endian
Instruction formats
Format 1Â : (used for register instructions)
| Offset | Size | Description |
|---|---|---|
| 0x0 | 0x6 | Operand descriptor ID (DESC) |
| 0x6 | 0x6 | Source 1 register (SRC2) |
| 0xC | 0x6 | Source 2 register (SRC1) |
| 0x12 | 0x2 | Flags |
| 0x24 | 0x2 | Destination register (DST) |
| 0x1A | 0x6 | Opcode |
Format 2Â : (used for flow control instructions)
| Offset | Size | Description |
|---|---|---|
| 0x0 | 0x8 | Number of instructions ? (NUM) |
| 0x8 | 0x10? | Destination offset (DST) |
| 0x1A | 0x6 | Opcode |
Instructions
| Opcode | Format | Name | Description |
|---|---|---|---|
| 0x02 | 1 | DP4 | Computes dot product on 4-component vectors; DST = SRC1.SRC2 |
| 0x13 | 1 | MOV | Moves value; DST = SRC1 |
| 0x24 | 1 | CALL | Jumps to DST and executes NUM instructions |
| 0x21 | 1 | END2 | ? |
| 0x22 | 1 | END1 | ? |
Operand descriptors
| Offset | Size | Description |
|---|---|---|
| 0x0 | 0x4 | Destination component mask. Bit 3 = x, 2 = y, 1 = z, 0 = w. |
| 0x5 | 0x8 | Source 1 component selector |
| 0x14 | 0x8 | Source 2 component selector |
| 0x1F | 0x1 | Flag |
Component selector :
| Offset | Size | Description |
|---|---|---|
| 0x0 | 0x2 | Component 3 value |
| 0x2 | 0x2 | Component 2 value |
| 0x4 | 0x2 | Component 1 value |
| 0x6 | 0x2 | Component 0 value |
| Value | Component |
|---|---|
| 0x0 | x |
| 0x1 | y |
| 0x2 | z |
| 0x3 | w |
The component selector enables swizzling. For example, component selector 0x1B is equivalent to .xyzw, while 0x55 is equivalent to .yyyy.