(this page is hugely WIP)
Overview
GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.
Types
There are three main types of registers :
- configuration registers, which directly map to various rendering properties (for example : GPUREG_FACECULLING_CONFIG)
- data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example : GPUREG_GSH_CODETRANSFER_DATA)
- action triggering registers, which tell the GPU to do something, like draw a primitive (for example : GPUREG_DRAWARRAYS)
Aliases
It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU Commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to GPUREG_VSH_FLOATUNIFORM_DATA so that a consecutively writing command based at 02C0 will write its first parameter to GPUREG_VSH_FLOATUNIFORM_CONFIG and ever subsequent ones to GPUREG_VSH_FLOATUNIFORM_DATA
Data Types
| Name
|
Description
|
| signed
|
Signed integer
|
| unsigned
|
Unsigned integer
|
| floatX.Y.Z
|
Floating-point number with X sign bits, Y exponent bits, and Z mantissa bits
|
| fixedX.Y.Z
|
Fixed-point number with X sign bits, Y integer bits, and Z fractional bits
|
Register list
Miscellaneous registers (0x000-0x03F)
Rasterizer registers (0x040-0x07F)
Texturing registers (0x080-0x0FF)
Framebuffer registers (0x100-0x13F)
Fragment lighting registers (0x140-0x1FF)
Geometry pipeline registers (0x200-0x27F)
Shader registers (0x280-0x2DF)
Unknown registers (0x2E0-0x2FF)
Miscellaneous registers
GPUREG_FINALIZE
| Bits
|
Description
|
| 0-31
|
unsigned, Trigger P3D Interrupt (0 = idle, non-zero = trigger)
|
Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.
Failure to write to this register in any command buffer will result in the GPU hanging.
Rasterizer registers
GPUREG_FACECULLING_CONFIG
| Bits
|
Description
|
| 0-1
|
unsigned, Culling mode
|
Culling mode values:
| Value
|
Description
|
| 0
|
None
|
| 1
|
Front Face (Counter Clockwise)
|
| 2
|
Back Face (Counter Clockwise)
|
GPUREG_VIEWPORT_WIDTH
| Bits
|
Description
|
| 0-23
|
float1.7.16, width / 2
|
GPUREG_VIEWPORT_INVW
| Bits
|
Description
|
| 1-31
|
float1.7.23, 2 / width
|
GPUREG_VIEWPORT_HEIGHT
| Bits
|
Description
|
| 0-23
|
float1.7.16, height / 2
|
GPUREG_VIEWPORT_INVH
| Bits
|
Description
|
| 1-31
|
float1.7.23, 2 / height
|
GPUREG_FRAGOP_CLIP
| Bits
|
Description
|
| 0
|
unsigned, Enabled (0 = disabled, 1 = enabled)
|
GPUREG_FRAGOP_CLIP_DATAi
| Bits
|
Description
|
| 0-23
|
float1.7.16, Clipping plane coefficient
|
GPUREG_DEPTHMAP_SCALE
| Bits
|
Description
|
| 0-23
|
float1.7.16, Near - Far
|
GPUREG_DEPTHMAP_OFFSET
| Bits
|
Description
|
| 0-23
|
float1.7.16, Near
|
GPUREG_SH_OUTMAP_TOTAL
| Bits
|
Description
|
| 0-2
|
unsigned, Number of following attributes
|
GPUREG_SH_OUTMAP_Oi
These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.
| Bits
|
Description
|
| 0-4
|
unsigned, Semantic for the x component of the register.
|
| 8-12
|
unsigned, Semantic for the y component of the register.
|
| 16-20
|
unsigned, Semantic for the z component of the register.
|
| 24-28
|
unsigned, Semantic for the w component of the register.
|
The semantic ids are:
| Value
|
Semantic
|
Description
|
| 0x00
|
position.x
|
Vertex Position
|
| 0x01
|
position.y
|
| 0x02
|
position.z
|
| 0x03
|
position.w
|
| 0x04
|
normquat.x
|
Quaternion specifying the normal/tangent frame (for fragment lighting)
|
| 0x05
|
normquat.y
|
| 0x06
|
normquat.z
|
| 0x07
|
normquat.w
|
| 0x08
|
color.r
|
Vertex color
|
| 0x09
|
color.g
|
| 0x0A
|
color.b
|
| 0x0B
|
color.a
|
| 0x0C
|
texcoord0.u
|
Texture coordinates for texture 0
|
| 0x0D
|
texcoord0.v
|
| 0x0E
|
texcoord1.u
|
Texture coordinates for texture 1
|
| 0x0F
|
texcoord1.v
|
| 0x10
|
texcoord0.w
|
|
| 0x12
|
view.x
|
View vector (for fragment lighting)
|
| 0x13
|
view.y
|
| 0x14
|
view.z
|
| 0x16
|
texcoord2.u
|
Texture coordinates for texture 2
|
| 0x17
|
texcoord2.v
|
| 0x1F
|
Unused component
|
Should be set for unused components of the output register
|
GPUREG_EARLYDEPTH_FUNC
| Bits
|
Description
|
| 0-1
|
unsigned, Early depth function
|
Early depth function values:
| Value
|
Description
|
| 0
|
>=
|
| 1
|
>
|
| 2
|
<=
|
| 3
|
<
|
GPUREG_EARLYDEPTH_TEST1
| Bits
|
Description
|
| 0
|
unsigned, Enabled (0 = disabled, 1 = enabled)
|
GPUREG_EARLYDEPTH_CLEAR
| Bits
|
Description
|
| 0
|
unsigned, Trigger (0 = idle, 1 = clear)
|
GPUREG_SH_OUTATTR_MODE
| Bits
|
Description
|
| 0
|
unsigned, Use texture coordinates (0 = don't use, 1 = use)
|
GPUREG_SCISSORTEST_MODE
| Bits
|
Description
|
| 0-1
|
unsigned, Enabled (0 = disabled, 3 = enabled)
|
GPUREG_SCISSORTEST_POS
| Bits
|
Description
|
| 0-9
|
unsigned, X1
|
| 16-25
|
unsigned, Y1
|
GPUREG_SCISSORTEST_DIM
| Bits
|
Description
|
| 0-9
|
unsigned, X2
|
| 16-25
|
unsigned, Y2
|
GPUREG_VIEWPORT_XY
| Bits
|
Description
|
| 0-9
|
unsigned, X
|
| 16-25
|
unsigned, Y
|
GPUREG_EARLYDEPTH_DATA
| Bits
|
Description
|
| 0-23
|
unsigned, Clear value
|
GPUREG_DEPTHMAP_ENABLE
| Bits
|
Description
|
| 0
|
unsigned, Enabled (0 = disabled, 1 = enabled)
|
GPUREG_RENDERBUF_DIM
| Bits
|
Description
|
| 0-10
|
unsigned, Width
|
| 12-21
|
unsigned, Height - 1
|
| 24
|
0x1
|
GPUREG_SH_OUTATTR_CLOCK
| Bits
|
Description
|
| 0
|
unsigned, 'position.z' present (0 = absent, 1 = present)
|
| 1
|
unsigned, 'color' component present (0 = absent, 1 = present)
|
| 8
|
unsigned, 'texcoord0' component present (0 = absent, 1 = present)
|
| 9
|
unsigned, 'texcoord1' component present (0 = absent, 1 = present)
|
| 10
|
unsigned, 'texcoord2' component present (0 = absent, 1 = present)
|
| 16
|
unsigned, 'texcoord0.w' present (0 = absent, 1 = present)
|
| 24
|
unsigned, 'normquat' or 'view' component present (0 = absent, 1 = present)
|
Texturing registers
GPUREG_TEXUNIT_CONFIG
| Bits
|
Description
|
| 0
|
unsigned, Texture 0 enabled (0 = disabled, 1 = enabled)
|
| 1
|
unsigned, Texture 1 enabled (0 = disabled, 1 = enabled)
|
| 2
|
unsigned, Texture 2 enabled (0 = disabled, 1 = enabled)
|
| 3
|
0x0
|
| 8-9
|
unsigned, Texture 3 coordinates
|
| 10
|
unsigned, Texture 3 enabled (0 = disabled, 1 = enabled)
|
| 12
|
0x1
|
| 13
|
unsigned, Texture 2 coordinates
|
| 16
|
unsigned, Clear texture cache (0 = don't clear, 1 = clear)
|
| 17
|
0x0
|
Texture 3 coordinates values:
| Value
|
Description
|
| 0
|
Texture 0
|
| 1
|
Texture 1
|
| 2
|
Texture 2
|
Texture 2 coordinates values:
| Value
|
Description
|
| 0
|
Texture 2
|
| 1
|
Texture 1
|
GPUREG_TEXUNITi_BORDER_COLOR
| Bits
|
Description
|
| 0-7
|
unsigned, Red
|
| 8-15
|
unsigned, Green
|
| 16-23
|
unsigned, Blue
|
| 24-31
|
unsigned, Alpha
|
GPUREG_TEXUNITi_DIM
| Bits
|
Description
|
| 0-10
|
unsigned, Height
|
| 16-26
|
unsigned, Width
|
GPUREG_TEXUNITi_PARAM
| Bits
|
Description
|
| 1
|
unsigned, Magnification filter
|
| 2
|
unsigned, Minification filter
|
| 4-5
|
unsigned, ETC1 (0 = not ETC1, 2 = ETC1)
|
| 8-10
|
unsigned, Wrap T
|
| 12-14
|
unsigned, Wrap S
|
| 16
|
0x0
|
| 20
|
unsigned, Shadow (Texture 0 only, 0 = not shadow, 1 = shadow)
|
| 24
|
unsigned, Mipmap filter
|
| 28-30
|
unsigned, Type (Texture 0 only)
|
Filter values:
| Value
|
Description
|
| 0
|
Nearest
|
| 1
|
Linear
|
Wrap values:
| Value
|
Description
|
| 0
|
Clamp to edge
|
| 1
|
Clamp to border
|
| 2
|
Repeat
|
| 3
|
Mirrored repeat
|
Type values:
| Value
|
Description
|
| 0
|
2D
|
| 1
|
Cube map
|
| 2
|
Shadow 2D
|
| 3
|
Projection
|
| 4
|
Shadow cube
|
| 5
|
Disabled
|
GPUREG_TEXUNITi_LOD
| Bits
|
Description
|
| 0-12
|
fixed1.4.8, Bias
|
| 16-19
|
unsigned, Max Level
|
| 24-27
|
unsigned, Min Level
|
GPUREG_TEXUNITi_ADDRi
First ADDR register:
| Bits
|
Description
|
| 0-27
|
unsigned, Texture physical address >> 3
|
Subsequent ADDR registers:
| Bits
|
Description
|
| 0-21
|
unsigned, Texture physical address >> 3 (upper 6 bits reused from first ADDR register)
|
If the texture is a cube:
| Register
|
Description
|
| ADDR1
|
Positive X
|
| ADDR2
|
Negative X
|
| ADDR3
|
Positive Y
|
| ADDR4
|
Negative Y
|
| ADDR5
|
Positive Z
|
| ADDR6
|
Negative Z
|
Otherwise, ADDR(1) points to a 2D texture, and the rest are empty.
GPUREG_TEXUNITi_SHADOW
| Bits
|
Description
|
| 0
|
unsigned, Perspective (0 = not perspective, 1 = perspective)
|
| 1-23
|
fixed0.0.24, Z bias (upper 23 bits)
|
GPUREG_TEXUNITi_TYPE
| Bits
|
Description
|
| 0-3
|
unsigned, Format
|
GPUREG_LIGHTING_ENABLE0
| Bits
|
Description
|
| 0
|
unsigned, Enabled (0 = disabled, 1 = enabled)
|
GPUREG_TEXUNIT3_PROCTEX0
| Bits
|
Description
|
| 0-2
|
unsigned, U-direction clamp
|
| 3-5
|
unsigned, V-direction clamp
|
| 6-9
|
unsigned, RGB mapping function
|
| 10-13
|
unsigned, Alpha mapping function
|
| 14
|
unsigned, Handle alpha separately (0 = don't separate, 1 = separate)
|
| 15
|
unsigned, Noise enabled (0 = disabled, 1 = enabled)
|
| 16-17
|
unsigned, U-direction shift
|
| 18-19
|
unsigned, V-direction shift
|
| 20-27
|
float1.5.10, Texture bias (lower 8 bits)
|
Clamp values:
| Value
|
Description
|
| 0
|
Clamp to zero
|
| 1
|
Clamp to edge
|
| 2
|
Symmetrical repeat
|
| 3
|
Mirrored repeat
|
| 4
|
Pulse
|
Mapping function values:
| Value
|
Description
|
| 0
|
U
|
| 1
|
U2
|
| 2
|
V
|
| 3
|
V2
|
| 4
|
U + V
|
| 5
|
U2 + V2
|
| 6
|
sqrt(U2 + V2)
|
| 7
|
Minimum
|
| 8
|
Maximum
|
| 9
|
Rmax
|
Shift values:
| Value
|
Description
|
| 0
|
None
|
| 1
|
Odd
|
| 2
|
Even
|
GPUREG_TEXUNIT3_PROCTEX1
| Bits
|
Description
|
| 0-15
|
fixed1.3.12, U-direction noise amplitude
|
| 16-31
|
float1.5.10, U-direction noise phase
|
GPUREG_TEXUNIT3_PROCTEX2
| Bits
|
Description
|
| 0-15
|
fixed1.3.12, V-direction noise amplitude
|
| 16-31
|
float1.5.10, V-direction noise phase
|
GPUREG_TEXUNIT3_PROCTEX3
| Bits
|
Description
|
| 0-15
|
float1.5.10, U-direction noise frequency
|
| 16-31
|
float1.5.10, V-direction noise frequency
|
GPUREG_TEXUNIT3_PROCTEX4
| Bits
|
Description
|
| 0-2
|
unsigned, Minification filter
|
| 3-10
|
0x60
|
| 11-18
|
unsigned, Texture width
|
| 19-26
|
float1.5.10, Texture bias (upper 8 bits)
|
Minification filter values:
| Value
|
Description
|
| 0
|
Nearest
|
| 1
|
Linear
|
| 2
|
Nearest, Mipmap Nearest
|
| 3
|
Linear, Mipmap Nearest
|
| 4
|
Nearest, Mipmap Linear
|
| 5
|
Linear, Mipmap Linear
|
GPUREG_TEXUNIT3_PROCTEX5
| Bits
|
Description
|
| 0-7
|
unsigned, Texture offset
|
| 8-31
|
0xE0C080
|
GPUREG_PROCTEX_LUT
| Bits
|
Description
|
| 0-7
|
unsigned, Index
|
| 8-11
|
unsigned, Reference table
|
Reference table values:
| Value
|
Description
|
| 0
|
Noise table
|
| 2
|
RGB mapping function table
|
| 3
|
Alpha mapping function table
|
| 4
|
Color table
|
| 5
|
Color difference table
|
GPUREG_PROCTEX_LUT_DATAi
| Bits
|
Description
|
| 0-31
|
LUT data
|
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the table selected with GPUREG_PROCTEX_LUT, starting at the selected index.
Noise Table
128 elements:
| Bits
|
Description
|
| 0-11
|
fixed0.0.12, Value
|
| 12-23
|
fixed1.0.11, Difference from next element
|
RGB Mapping Function Table
128 elements:
| Bits
|
Description
|
| 0-11
|
fixed0.0.12, Value
|
| 12-23
|
fixed1.0.11, Difference from next element
|
Alpha Mapping Function Table
128 elements:
| Bits
|
Description
|
| 0-11
|
fixed0.0.12, Value
|
| 12-23
|
fixed1.0.11, Difference from next element
|
Color Table
256 elements:
| Bits
|
Description
|
| 0-7
|
unsigned, Red
|
| 8-15
|
unsigned, Green
|
| 16-23
|
unsigned, Blue
|
| 24-31
|
unsigned, Alpha
|
Color Difference Table
256 elements:
| Bits
|
Description
|
| 0-7
|
fixed1.0.7, Red difference between current and next color table elements
|
| 8-15
|
fixed1.0.7, Green difference between current and next color table elements
|
| 16-23
|
fixed1.0.7, Blue difference between current and next color table elements
|
| 24-31
|
fixed1.0.7, Alpha difference between current and next color table elements
|
GPUREG_TEXENVi_SOURCE
| Bits
|
Description
|
| 0-3
|
unsigned, RGB source 0
|
| 4-7
|
unsigned, RGB source 1
|
| 8-11
|
unsigned, RGB source 2
|
| 16-19
|
unsigned, Alpha source 0
|
| 20-23
|
unsigned, Alpha source 1
|
| 24-27
|
unsigned, Alpha source 2
|
Source values:
| Value
|
Description
|
| 0
|
Primary color
|
| 1
|
Fragment primary color
|
| 2
|
Fragment secondary color
|
| 3
|
Texture 0
|
| 4
|
Texture 1
|
| 5
|
Texture 2
|
| 6
|
Texture 3
|
| 13
|
Previous buffer
|
| 14
|
Constant (from GPUREG_TEXENVi_COLOR)
|
| 15
|
Previous
|
GPUREG_TEXENVi_OPERAND
| Bits
|
Description
|
| 0-3
|
unsigned, RGB operand 0
|
| 4-7
|
unsigned, RGB operand 1
|
| 8-11
|
unsigned, RGB operand 2
|
| 12-14
|
unsigned, Alpha operand 0
|
| 16-18
|
unsigned, Alpha operand 1
|
| 20-22
|
unsigned, Alpha operand 2
|
RGB operand values:
| Value
|
Description
|
| 0
|
Source color
|
| 1
|
One minus source color
|
| 2
|
Source alpha
|
| 3
|
One minus source alpha
|
| 4
|
Source red
|
| 5
|
One minus source red
|
| 8
|
Source green
|
| 9
|
One minus source green
|
| 12
|
Source blue
|
| 13
|
One minus source blue
|
Alpha operand values:
| Value
|
Description
|
| 0
|
Source alpha
|
| 1
|
One minus source alpha
|
| 2
|
Source red
|
| 3
|
One minus source red
|
| 4
|
Source green
|
| 5
|
One minus source green
|
| 6
|
Source blue
|
| 7
|
One minus source blue
|
GPUREG_TEXENVi_COMBINER
| Bits
|
Description
|
| 0-3
|
unsigned, RGB combine
|
| 16-19
|
unsigned, Alpha combine
|
Combine values:
| Value
|
Description
|
| 0
|
Replace
|
| 1
|
Modulate
|
| 2
|
Add
|
| 3
|
Add signed
|
| 4
|
Interpolate
|
| 5
|
Subtract
|
| 6
|
Dot3 RGB
|
| 7
|
Dot3 RGBA
|
| 8
|
Multiply then add
|
| 9
|
Add then multiply
|
GPUREG_TEXENVi_COLOR
| Bits
|
Description
|
| 0-7
|
unsigned, Red
|
| 8-15
|
unsigned, Green
|
| 16-23
|
unsigned, Blue
|
| 24-31
|
unsigned, Alpha
|
GPUREG_TEXENVi_SCALE
| Bits
|
Description
|
| 0-1
|
unsigned, RGB scale
|
| 16-17
|
unsigned, Alpha scale
|
Scale values:
| Value
|
Description
|
| 0
|
1x
|
| 1
|
2x
|
| 2
|
4x
|
GPUREG_TEXENV_UPDATE_BUFFER
| Bits
|
Description
|
| 0-2
|
unsigned, Fog mode
|
| 3
|
unsigned, Shading density source
|
| 8
|
unsigned, TexEnv 1 RGB buffer input
|
| 9
|
unsigned, TexEnv 2 RGB buffer input
|
| 10
|
unsigned, TexEnv 3 RGB buffer input
|
| 11
|
unsigned, TexEnv 4 RGB buffer input
|
| 12
|
unsigned, TexEnv 1 alpha buffer input
|
| 13
|
unsigned, TexEnv 2 alpha buffer input
|
| 14
|
unsigned, TexEnv 3 alpha buffer input
|
| 15
|
unsigned, TexEnv 4 alpha buffer input
|
| 16
|
unsigned, Z flip (0 = don't flip, 1 = flip)
|
| 24-25
|
0x0
|
This register is shared between the gas/fog mode configuration and TexEnv buffer inputs. TexEnv buffer inputs are typically written with a mask of 0x2, and the gas/fog mode configuration is typically written with a mask of 0x5.
Fog mode values:
| Value
|
Description
|
| 0
|
Disabled
|
| 5
|
Fog
|
| 7
|
Gas
|
Shading density source values:
| Value
|
Description
|
| 0
|
Plain density
|
| 1
|
Depth density
|
Buffer input values:
| Value
|
Description
|
| 0
|
Previous buffer
|
| 1
|
Previous
|
GPUREG_FOG_COLOR
| Bits
|
Description
|
| 0-7
|
unsigned, Red
|
| 8-15
|
unsigned, Green
|
| 16-23
|
unsigned, Blue
|
GPUREG_GAS_ATTENUATION
| Bits
|
Description
|
| 0-15
|
float1.5.10, Gas density attenuation
|
GPUREG_GAS_ACCMAX
| Bits
|
Description
|
| 0-15
|
float1.5.10, Gas maximum density accumulation
|
GPUREG_FOG_LUT_INDEX
| Bits
|
Description
|
| 0-15
|
unsigned, Index
|
GPUREG_FOG_LUT_DATAi
| Bits
|
Description
|
| 0-23
|
LUT data
|
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the fog look-up table, starting at the index selected with GPUREG_FOG_LUT_INDEX.
Fog Look-Up Table
128 elements:
| Bits
|
Description
|
| 0-12
|
fixed1.1.11, Difference from next element
|
| 13-23
|
fixed0.0.11, Value
|
GPUREG_TEXENV_BUFFER_COLOR
| Bits
|
Description
|
| 0-7
|
unsigned, Red
|
| 8-15
|
unsigned, Green
|
| 16-23
|
unsigned, Blue
|
| 24-31
|
unsigned, Alpha
|
Framebuffer registers
GPUREG_COLOR_OPERATION
| Bits
|
Description
|
| 0-1
|
unsigned, Fragment operation mode
|
| 8
|
unsigned, Blend mode
|
| 16-25
|
0x0E4
|
Fragment operation mode values:
| Value
|
Description
|
| 0
|
Default
|
| 1
|
Gas
|
| 3
|
Shadow
|
Blend mode values:
| Value
|
Description
|
| 0
|
Logic op
|
| 1
|
Blend
|
GPUREG_BLEND_FUNC
| Bits
|
Description
|
| 0-2
|
unsigned, RGB equation
|
| 8-10
|
unsigned, Alpha equation
|
| 16-19
|
unsigned, RGB source function
|
| 20-23
|
unsigned, RGB destination function
|
| 24-27
|
unsigned, Alpha source function
|
| 28-31
|
unsigned, Alpha destination function
|
Equation values:
| Value
|
Description
|
| 0
|
Add
|
| 1
|
Subtract
|
| 2
|
Reverse subtract
|
| 3
|
Minimum
|
| 4
|
Maximum
|
Function values:
| Value
|
Description
|
| 0
|
Zero
|
| 1
|
One
|
| 2
|
Source color
|
| 3
|
One minus source color
|
| 4
|
Destination color
|
| 5
|
One minus destination color
|
| 6
|
Source alpha
|
| 7
|
One minus source alpha
|
| 8
|
Destination alpha
|
| 9
|
One minus destination alpha
|
| 10
|
Constant color
|
| 11
|
One minus constant color
|
| 12
|
Constant alpha
|
| 13
|
One minus constant alpha
|
| 14
|
Source alpha saturate
|
GPUREG_LOGIC_OP
| Bits
|
Description
|
| 0-3
|
unsigned, Logic op
|
Logic op values:
| Value
|
Description
|
| 0
|
Clear
|
| 1
|
AND
|
| 2
|
Reverse AND
|
| 3
|
Copy
|
| 4
|
Set
|
| 5
|
Inverted copy
|
| 6
|
Noop
|
| 7
|
Invert
|
| 8
|
NAND
|
| 9
|
OR
|
| 10
|
NOR
|
| 11
|
XOR
|
| 12
|
Equivalent
|
| 13
|
Inverted AND
|
| 14
|
Reverse OR
|
| 15
|
Inverted OR
|
GPUREG_BLEND_COLOR
| Bits
|
Description
|
| 0-7
|
unsigned, Red
|
| 8-15
|
unsigned, Green
|
| 16-23
|
unsigned, Blue
|
| 24-31
|
unsigned, Alpha
|
GPUREG_FRAGOP_ALPHA_TEST
| Bits
|
Description
|
| 0
|
unsigned, Enabled (0 = disabled, 1 = enabled)
|
| 4-6
|
unsigned, Function
|
| 8-15
|
unsigned, Reference value
|
Function values:
| Value
|
Description
|
| 0
|
Never
|
| 1
|
Always
|
| 2
|
Equal
|
| 3
|
Not equal
|
| 4
|
Less than
|
| 5
|
Less than or equal
|
| 6
|
Greater than
|
| 7
|
Greater than or equal
|
GPUREG_STENCIL_TEST
| Bits
|
Description
|
| 0
|
unsigned, Enabled (0 = disabled, 1 = enabled)
|
| 4-6
|
unsigned, Function
|
| 8-15
|
unsigned, Buffer mask
|
| 16-23
|
signed, Reference value
|
| 24-31
|
unsigned, Mask
|
Function values:
| Value
|
Description
|
| 0
|
Never
|
| 1
|
Always
|
| 2
|
Equal
|
| 3
|
Not equal
|
| 4
|
Less than
|
| 5
|
Less than or equal
|
| 6
|
Greater than
|
| 7
|
Greater than or equal
|
GPUREG_STENCIL_OP
| Bits
|
Description
|
| 0-2
|
unsigned, Fail operation
|
| 4-6
|
unsigned, Z-fail operation
|
| 8-10
|
unsigned, Z-pass operation
|
Operation values:
| Value
|
Description
|
| 0
|
Keep
|
| 1
|
Zero
|
| 2
|
Replace
|
| 3
|
Increment
|
| 4
|
Decrement
|
| 5
|
Invert
|
| 6
|
Increment and wrap
|
| 7
|
Decrement and wrap
|
GPUREG_DEPTH_COLOR_MASK
| Bits
|
Description
|
| 0
|
unsigned, Depth test enabled (0 = disabled, 1 = enabled)
|
| 4-6
|
unsigned, Depth function
|
| 8
|
unsigned, Red write enabled (0 = disabled, 1 = enabled)
|
| 9
|
unsigned, Green write enabled (0 = disabled, 1 = enabled)
|
| 10
|
unsigned, Blue write enabled (0 = disabled, 1 = enabled)
|
| 11
|
unsigned, Alpha write enabled (0 = disabled, 1 = enabled)
|
| 12
|
unsigned, Depth write enabled (0 = disabled, 1 = enabled)
|
Depth function values:
| Value
|
Description
|
| 0
|
Never
|
| 1
|
Always
|
| 2
|
Equal
|
| 3
|
Not equal
|
| 4
|
Less than
|
| 5
|
Less than or equal
|
| 6
|
Greater than
|
| 7
|
Greater than or equal
|
GPUREG_FRAMEBUFFER_INVALIDATE
| Bits
|
Description
|
| 0
|
unsigned, Trigger (0 = idle, 1 = invalidate)
|
| 1-31
|
0x0
|
Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does not flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.
GPUREG_FRAMEBUFFER_FLUSH
| Bits
|
Description
|
| 0
|
unsigned, Trigger (0 = idle, 1 = flush)
|
| 1-31
|
0x0
|
Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.
GPUREG_COLORBUFFER_READ
| Bits
|
Description
|
| 0-3
|
unsigned, Allow read (0 = disable, 0xF = enable)
|
GPUREG_COLORBUFFER_WRITE
| Bits
|
Description
|
| 0-3
|
unsigned, Allow write (0 = disable, 0xF = enable)
|
GPUREG_DEPTHBUFFER_READ
| Bits
|
Description
|
| 0
|
unsigned, Allow stencil read (0 = disable, 1 = enable)
|
| 1
|
unsigned, Allow depth read (0 = disable, 1 = enable)
|
GPUREG_DEPTHBUFFER_WRITE
| Bits
|
Description
|
| 0
|
unsigned, Allow stencil write (0 = disable, 1 = enable)
|
| 1
|
unsigned, Allow depth write (0 = disable, 1 = enable)
|
GPUREG_DEPTHBUFFER_FORMAT
| Bits
|
Description
|
| 0-1
|
unsigned, Format
|
Format values:
| Value
|
Description
|
| 0
|
16-bit depth
|
| 2
|
24-bit depth
|
| 3
|
24-bit depth + 8-bit stencil
|
GPUREG_COLORBUFFER_FORMAT
| Bits
|
Description
|
| 0-1
|
unsigned, Pixel size
|
| 16-18
|
unsigned, Format
|
Pixel size values:
| Value
|
Description
|
| 0
|
16-bit color
|
| 2
|
32-bit color
|
Format values:
| Value
|
Description
|
| 0
|
RGBA8/Gas
|
| 2
|
RGB5A1
|
| 3
|
RGB565
|
| 4
|
RGBA4
|
Color components are laid out in reverse byte order in memory, with the most significant bits used first.
GPUREG_EARLYDEPTH_TEST2
| Bits
|
Description
|
| 0
|
unsigned, Enabled (0 = disabled, 1 = enabled)
|
GPUREG_FRAMEBUFFER_BLOCK32
| Bits
|
Description
|
| 0
|
unsigned, Render block mode
|
To untile the color buffer when using the 32x32 block format, use bit 16 of the display transfer flags. It is unknown if there are any advantages to using the 32x32 format.
Render block mode values:
| Value
|
Description
|
| 0
|
8x8 blocks
|
| 1
|
32x32 blocks
|
GPUREG_DEPTHBUFFER_LOC
| Bits
|
Description
|
| 0-27
|
unsigned, Depth buffer physical address >> 3
|
GPUREG_COLORBUFFER_LOC
| Bits
|
Description
|
| 0-27
|
unsigned, Color buffer physical address >> 3
|
GPUREG_FRAMEBUFFER_DIM
| Bits
|
Description
|
| 0-10
|
unsigned, Width
|
| 12-21
|
unsigned, Height - 1
|
| 24
|
0x1
|
GPUREG_GAS_LIGHT_XY
| Bits
|
Description
|
| 0-7
|
unsigned, Planar shading minimum intensity
|
| 8-15
|
unsigned, Planar shading maximum intensity
|
| 16-23
|
unsigned, Planar shading density attenuation
|
GPUREG_GAS_LIGHT_Z
| Bits
|
Description
|
| 0-7
|
unsigned, View shading minimum intensity
|
| 8-15
|
unsigned, View shading maximum intensity
|
| 16-23
|
unsigned, View shading density attenuation
|
GPUREG_GAS_LIGHT_Z_COLOR
| Bits
|
Description
|
| 0-7
|
unsigned, View shading effect in line-of-sight direction
|
GPUREG_GAS_LUT_INDEX
| Bits
|
Description
|
| 0-15
|
unsigned, Index
|
GPUREG_GAS_LUT_DATA
| Bits
|
Description
|
| 0-31
|
LUT data
|
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAAS_LUT_INDEX.
Gas Look-Up Table
16 elements:
First 8 elements:
| Bits
|
Description
|
| 0-7
|
signed, Red
|
| 8-15
|
signed, Green
|
| 16-23
|
signed, Blue
|
Last 8 elements:
| Bits
|
Description
|
| 0-7
|
unsigned, Red
|
| 8-15
|
unsigned, Green
|
| 16-23
|
unsigned, Blue
|
GPUREG_GAS_DELTAZ_DEPTH
| Bits
|
Description
|
| 0-23
|
fixed0.16.8, Depth direction attenuation proportion
|
GPUREG_FRAGOP_SHADOW
| Bits
|
Description
|
| 0-15
|
float1.5.10, Sum of penumbra scale and penumbra bias
|
| 16-31
|
float1.5.10, Penumbra scale with reversed sign
|
Fragment lighting registers
GPUREG_LIGHTi_SPECULAR0
| Bits
|
Description
|
| 0-7
|
unsigned, Blue
|
| 10-17
|
unsigned, Green
|
| 20-27
|
unsigned, Red
|
These registers contain the specular0 color of the corresponding light. Usually set to material_specular0*lightX_specular0.
GPUREG_LIGHTi_SPECULAR1
| Bits
|
Description
|
| 0-7
|
unsigned, Blue
|
| 10-17
|
unsigned, Green
|
| 20-27
|
unsigned, Red
|
These registers contain the specular1 color of the corresponding light. Usually set to material_specular1*lightX_specular1.
GPUREG_LIGHTi_DIFFUSE
| Bits
|
Description
|
| 0-7
|
unsigned, Blue
|
| 10-17
|
unsigned, Green
|
| 20-27
|
unsigned, Red
|
These registers contain the diffuse color of the corresponding light. Usually set to material_diffuse*lightX_diffuse.
GPUREG_LIGHTi_AMBIENT
| Bits
|
Description
|
| 0-7
|
unsigned, Blue
|
| 10-17
|
unsigned, Green
|
| 20-27
|
unsigned, Red
|
These registers contain the ambient color of the corresponding light. Usually set to material_ambient*lightX_ambient.
GPUREG_LIGHTi_XY
| Bits
|
Description
|
| 0-15
|
float1.5.10, X coordinate
|
| 16-31
|
float1.5.10, Y coordinate
|
These registers (along with _Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.
GPUREG_LIGHTi_Z
| Bits
|
Description
|
| 0-15
|
float1.5.10, Z coordinate
|
These registers (along with _XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.
GPUREG_LIGHTi_SPOTDIR_XY
| Bits
|
Description
|
| 0-12
|
fixed1.1.11, X coordinate (Usually the input value is negated)
|
| 16-28
|
fixed1.1.11, Y coordinate (Usually the input value is negated)
|
These registers (along with _Z) represent the spot direction (unitary) vector of the corresponding light.
GPUREG_LIGHTi_SPOTDIR_Z
| Bits
|
Description
|
| 0-12
|
fixed1.1.11, Z coordinate (Usually the input value is negated)
|
These registers (along with _XY) represent the spot direction (unitary) vector of the corresponding light.
GPUREG_LIGHTi_CONFIG
| Bits
|
Description
|
| 0
|
unsigned, Light type (0 = positional light, 1 = directional light)
|
| 1
|
unsigned, Two side diffuse (0 = one side, 1 = both sides)
|
| 2
|
unsigned, Use geometric factor 0 (0 = don't use, 1 = use)
|
| 3
|
unsigned, Use geometric factor 1 (0 = don't use, 1 = use)
|
GPUREG_LIGHTi_ATTENUATION_BIAS
| Bits
|
Description
|
| 0-19
|
float1.7.12, Distance attenuation bias
|
These registers contain the distance attenuation bias value of the corresponding light. The attenuation factor is lut_DA(clip(bias + scale*distance, 0.0, 1.0)).
GPUREG_LIGHTi_ATTENUATION_SCALE
| Bits
|
Description
|
| 0-19
|
float1.7.12, Distance attenuation scale
|
These registers contain the distance attenuation scale value of the corresponding light. The attenuation factor is lut_DA(clip(bias + scale*distance, 0.0, 1.0)).
GPUREG_LIGHTING_AMBIENT
| Bits
|
Description
|
| 0-7
|
unsigned, Blue
|
| 10-17
|
unsigned, Green
|
| 20-27
|
unsigned, Red
|
This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.
GPUREG_LIGHTING_NUM_LIGHTS
| Bits
|
Description
|
| 0-2
|
unsigned, Number of active lights - 1
|
GPUREG_LIGHTING_CONFIG0
| Bits
|
Description
|
| 0
|
unsigned, Shadow factor enabled (0 = disabled, 1 = enabled) (usually accompanied by bit 16, 17, or 18)
|
| 2-3
|
unsigned, Fresnel selector
|
| 4-7
|
unsigned, Light environment configuration
|
| 8-11
|
0x4
|
| 16
|
unsigned, Apply shadow attenuation to primary color (0 = don't apply, 1 = apply)
|
| 17
|
unsigned, Apply shadow attenuation to secondary color (0 = don't apply, 1 = apply)
|
| 18
|
unsigned, Invert shadow attenuation (0 = don't invert, 1 = invert)
|
| 19
|
unsigned, Apply shadow attenuation to alpha component (0 = don't apply, 1 = apply)
|
| 22-23
|
unsigned, Bump map texture unit
|
| 24-25
|
unsigned, Shadow map texture unit
|
| 27
|
unsigned, Clamp highlights (0 = disabled, 1 = enabled)
|
| 28-29
|
unsigned, Bump mode
|
| 30
|
unsigned, Recalculate bump vectors (0 = enabled, 1 = disabled) (usually set to 1 when bump mode is not 0)
|
| 31
|
0x1
|
Fresnel selector values:
| Value
|
Description
|
| 0
|
None
|
| 1
|
Primary alpha
|
| 2
|
Secondary alpha
|
| 3
|
Primary and secondary alpha
|
The light environment configuration controls which LUTs are available for use. If a LUT is not available in the selected configuration, its value will always read a constant 1.0 regardless of the enable state in GPUREG_LIGHTING_CONFIG1. If RR is enabled but not RG or RB, the output of RR is used for the three components; Red, Green and Blue.
Light environment configuration values:
| Value
|
Description
|
Available LUTs
|
| 0
|
Configuration 0
|
D0, RR, SP, DA
|
| 1
|
Configuration 1
|
FR, RR, SP, DA
|
| 2
|
Configuration 2
|
D0, D1, RR, DA
|
| 3
|
Configuration 3
|
D0, D1, FR, DA
|
| 4
|
Configuration 4
|
All except for FR
|
| 5
|
Configuration 5
|
All except for D1
|
| 6
|
Configuration 6
|
All except for RB and RG
|
| 8
|
Configuration 7
|
All
|
Bump mode values:
| Value
|
Description
|
| 0
|
Not used
|
| 1
|
Use as bump map
|
| 2
|
Use as tangent map
|
GPUREG_LIGHTING_CONFIG1
| Bits
|
Description
|
| 0
|
unsigned, Fragment light source 0 shadows disabled (0 = enabled, 1 = disabled)
|
| 1
|
unsigned, Fragment light source 1 shadows disabled (0 = enabled, 1 = disabled)
|
| 2
|
unsigned, Fragment light source 2 shadows disabled (0 = enabled, 1 = disabled)
|
| 3
|
unsigned, Fragment light source 3 shadows disabled (0 = enabled, 1 = disabled)
|
| 4
|
unsigned, Fragment light source 4 shadows disabled (0 = enabled, 1 = disabled)
|
| 5
|
unsigned, Fragment light source 5 shadows disabled (0 = enabled, 1 = disabled)
|
| 6
|
unsigned, Fragment light source 6 shadows disabled (0 = enabled, 1 = disabled)
|
| 7
|
unsigned, Fragment light source 7 shadows disabled (0 = enabled, 1 = disabled)
|
| 8
|
unsigned, Fragment light source 0 spot light disabled (0 = enabled, 1 = disabled)
|
| 9
|
unsigned, Fragment light source 1 spot light disabled (0 = enabled, 1 = disabled)
|
| 10
|
unsigned, Fragment light source 2 spot light disabled (0 = enabled, 1 = disabled)
|
| 11
|
unsigned, Fragment light source 3 spot light disabled (0 = enabled, 1 = disabled)
|
| 12
|
unsigned, Fragment light source 4 spot light disabled (0 = enabled, 1 = disabled)
|
| 13
|
unsigned, Fragment light source 5 spot light disabled (0 = enabled, 1 = disabled)
|
| 14
|
unsigned, Fragment light source 6 spot light disabled (0 = enabled, 1 = disabled)
|
| 15
|
unsigned, Fragment light source 7 spot light disabled (0 = enabled, 1 = disabled)
|
| 16
|
unsigned, Term 0 distribution component D0 LUT disabled (0 = enabled, 1 = disabled)
|
| 17
|
unsigned, Term 1 distribution component D1 LUT disabled (0 = enabled, 1 = disabled)
|
| 18
|
0x1
|
| 19
|
unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)
|
| 20-22
|
unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 7 = disabled)
|
| 21
|
unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 7 = disabled)
|
| 22
|
unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 7 = disabled)
|
| 24
|
unsigned, Fragment light source 0 distance attenuation disabled (0 = enabled, 1 = disabled)
|
| 25
|
unsigned, Fragment light source 1 distance attenuation disabled (0 = enabled, 1 = disabled)
|
| 26
|
unsigned, Fragment light source 2 distance attenuation disabled (0 = enabled, 1 = disabled)
|
| 27
|
unsigned, Fragment light source 3 distance attenuation disabled (0 = enabled, 1 = disabled)
|
| 28
|
unsigned, Fragment light source 4 distance attenuation disabled (0 = enabled, 1 = disabled)
|
| 29
|
unsigned, Fragment light source 5 distance attenuation disabled (0 = enabled, 1 = disabled)
|
| 30
|
unsigned, Fragment light source 6 distance attenuation disabled (0 = enabled, 1 = disabled)
|
| 31
|
unsigned, Fragment light source 7 distance attenuation disabled (0 = enabled, 1 = disabled)
|
GPUREG_LIGHTING_LUT_INDEX
| Bits
|
Description
|
| 0-7
|
unsigned, Starting index
|
| 8-12
|
unsigned, Look-up table
|
This register controls which LUT and what offset into it the LUT_DATA register writes to.
Lookup table values:
| Value
|
Description
|
| 0
|
D0
|
| 1
|
D1
|
| 3
|
FR
|
| 4
|
RB
|
| 5
|
RG
|
| 6
|
RR
|
| 8-15
|
SP0-7
|
| 16-23
|
DA0-7
|
GPUREG_LIGHTING_ENABLE1
| Bits
|
Description
|
| 0
|
unsigned, Disabled (0 = enabled, 1 = disabled)
|
This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.
GPUREG_LIGHTING_LUT_DATAi
| Bits
|
Description
|
| 0-23
|
LUT data
|
Lighting LUT data is written here.
A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.
DA: The input domain is [0.0, 1.0], and the index is an unsigned 8-bit number [0, 255] instead.
Format of an entry:
| Bits
|
Description
|
| 0-11
|
fixed0.0.12, Entry value
|
| 12-23
|
fixed1.0.11, Absolute value of the difference between the next entry and this entry, used to implement linear interpolation
|
GPUREG_LIGHTING_LUTINPUT_ABS
| Bits
|
Description
|
| 1
|
unsigned, abs() flag for the input of D0 (0 = enabled, 1 = disabled)
|
| 5
|
unsigned, abs() flag for the input of D1 (0 = enabled, 1 = disabled)
|
| 9
|
unsigned, abs() flag for the input of SP (0 = enabled, 1 = disabled)
|
| 13
|
unsigned, abs() flag for the input of FR (0 = enabled, 1 = disabled)
|
| 17
|
unsigned, abs() flag for the input of RB (0 = enabled, 1 = disabled)
|
| 21
|
unsigned, abs() flag for the input of RG (0 = enabled, 1 = disabled)
|
| 25
|
unsigned, abs() flag for the input of RR (0 = enabled, 1 = disabled)
|
This register controls whether the absolute value of the input is taken before using a LUT.
GPUREG_LIGHTING_LUTINPUT_SELECT
| Bits
|
Description
|
| 0-2
|
unsigned, Input selector for D0
|
| 4-6
|
unsigned, Input selector for D1
|
| 8-10
|
unsigned, Input selector for SP
|
| 12-14
|
unsigned, Input selector for FR
|
| 16-18
|
unsigned, Input selector for RB
|
| 20-22
|
unsigned, Input selector for RG
|
| 24-26
|
unsigned, Input selector for RR
|
Input selector values:
| Value
|
Description
|
| 0
|
N·H
|
| 1
|
V·H
|
| 2
|
N·V
|
| 3
|
L·N
|
| 4
|
-L·P (aka Spotlight aka SP)
|
| 5
|
cos Ï (aka CP)
|
GPUREG_LIGHTING_LUTINPUT_SCALE
| Bits
|
Description
|
| 0-2
|
unsigned, Scaler selector for D0
|
| 4-6
|
unsigned, Scaler selector for D1
|
| 8-10
|
unsigned, Scaler selector for SP
|
| 12-14
|
unsigned, Scaler selector for FR
|
| 16-18
|
unsigned, Scaler selector for RB
|
| 20-22
|
unsigned, Scaler selector for RG
|
| 24-26
|
unsigned, Scaler selector for RR
|
This register controls the scaling that is applied to the output of a LUT.
Scaler selector values:
| Value
|
Description
|
| 0
|
1x
|
| 1
|
2x
|
| 2
|
4x
|
| 3
|
8x
|
| 6
|
0.25x
|
| 7
|
0.5x
|
GPUREG_LIGHTING_LIGHT_PERMUTATION
| Bits
|
Description
|
| 0-2
|
unsigned, ID of the 1st enabled light
|
| 4-6
|
unsigned, ID of the 2nd enabled light
|
| 8-10
|
unsigned, ID of the 3rd enabled light
|
| 12-14
|
unsigned, ID of the 4th enabled light
|
| 16-18
|
unsigned, ID of the 5th enabled light
|
| 20-22
|
unsigned, ID of the 6th enabled light
|
| 24-26
|
unsigned, ID of the 7th enabled light
|
| 28-30
|
unsigned, ID of the 8th enabled light
|
Geometry pipeline registers
GPUREG_ATTRIBBUFFERS_LOC
| Bits
|
Description
|
| 1-28
|
unsigned, Vertex arrays base address
|
GPUREG_ATTRIBBUFFERS_FORMAT_LOW
| Bits
|
Description
|
| 0-1
|
unsigned, Vertex attribute 0 type
|
| 2-3
|
unsigned, Vertex attribute 0 size
|
| 4-5
|
unsigned, Vertex attribute 1 type
|
| 6-7
|
unsigned, Vertex attribute 1 size
|
| 8-9
|
unsigned, Vertex attribute 2 type
|
| 10-11
|
unsigned, Vertex attribute 2 size
|
| 12-13
|
unsigned, Vertex attribute 3 type
|
| 14-15
|
unsigned, Vertex attribute 3 size
|
| 16-17
|
unsigned, Vertex attribute 4 type
|
| 18-19
|
unsigned, Vertex attribute 4 size
|
| 20-21
|
unsigned, Vertex attribute 5 type
|
| 22-23
|
unsigned, Vertex attribute 5 size
|
| 24-25
|
unsigned, Vertex attribute 6 type
|
| 26-27
|
unsigned, Vertex attribute 6 size
|
| 28-29
|
unsigned, Vertex attribute 7 type
|
| 30-31
|
unsigned, Vertex attribute 7 size
|
Vertex attribute type values:
| Value
|
Description
|
| 0
|
Byte
|
| 1
|
Unsigned byte
|
| 2
|
Short
|
| 3
|
Float
|
Vertex attribute size values:
| Value
|
Description
|
| 0
|
8 bits
|
| 1
|
16 bits
|
| 2
|
24 bits
|
| 3
|
32 bits
|
GPUREG_ATTRIBBUFFERS_FORMAT_HIGH
| Bits
|
Description
|
| 0-1
|
unsigned, Vertex attribute 8 type
|
| 2-3
|
unsigned, Vertex attribute 8 size
|
| 4-5
|
unsigned, Vertex attribute 9 type
|
| 6-7
|
unsigned, Vertex attribute 9 size
|
| 8-9
|
unsigned, Vertex attribute 10 type
|
| 10-11
|
unsigned, Vertex attribute 10 size
|
| 12-13
|
unsigned, Vertex attribute 11 type
|
| 14-15
|
unsigned, Vertex attribute 11 size
|
| 16-27
|
unsigned, Fixed vertex attribute mask
|
| 28-31
|
unsigned, Total vertex attribute count - 1
|
See GPUREG_ATTRIBBUFFERS_FORMAT_LOW for vertex attribute type and size values.
GPUREG_ATTRIBBUFFERi_OFFSET
| Bits
|
Description
|
| 0-27
|
unsigned, Offset from base vertex arrays address
|
GPUREG_ATTRIBBUFFERi_CONFIG1
| Bits
|
Description
|
| 0-3
|
unsigned, Component 1
|
| 4-7
|
unsigned, Component 2
|
| 8-11
|
unsigned, Component 3
|
| 12-15
|
unsigned, Component 4
|
| 16-19
|
unsigned, Component 5
|
| 20-23
|
unsigned, Component 6
|
| 24-27
|
unsigned, Component 7
|
| 28-31
|
unsigned, Component 8
|
Component values:
| Value
|
Description
|
| 0
|
Vertex attribute 0
|
| 1
|
Vertex attribute 1
|
| 2
|
Vertex attribute 2
|
| 3
|
Vertex attribute 3
|
| 4
|
Vertex attribute 4
|
| 5
|
Vertex attribute 5
|
| 6
|
Vertex attribute 6
|
| 7
|
Vertex attribute 7
|
| 8
|
Vertex attribute 8
|
| 9
|
Vertex attribute 9
|
| 10
|
Vertex attribute 10
|
| 11
|
Vertex attribute 11
|
| 12
|
4-byte padding
|
| 13
|
8-byte padding
|
| 14
|
12-byte padding
|
| 15
|
16-byte padding
|
GPUREG_ATTRIBBUFFERi_CONFIG2
| Bits
|
Description
|
| 0-3
|
unsigned, Component 9
|
| 4-7
|
unsigned, Component 10
|
| 8-11
|
unsigned, Component 11
|
| 12-15
|
unsigned, Component 12
|
| 16-23
|
unsigned, Bytes per vertex
|
| 28-31
|
unsigned, Total number of components
|
See GPUREG_ATTRIBBUFFERi_CONFIG1 for component values.
GPUREG_INDEXBUFFER_CONFIG
| Bits
|
Description
|
| 0-27
|
unsigned, Offset from base vertex arrays address
|
| 31
|
Index type (0 = unsigned byte, 1 = unsigned short or drawing arrays)
|
GPUREG_NUMVERTICES
| Bits
|
Description
|
| 0-31
|
unsigned, Number of vertices to render
|
GPUREG_GEOSTAGE_CONFIG
| Bits
|
Description
|
| 0-1
|
unsigned, Geometry shader in use (0 = not in use, 2 = in use)
|
| 8
|
unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|
| 9
|
0x0
|
| 16-23
|
0x0
|
| 31
|
unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use)
|
This register configures the geometry stage of the GPU pipeline.
GPUREG_VERTEX_OFFSET
| Bits
|
Description
|
| 0-31
|
unsigned, Starting vertex offset
|
GPUREG_POST_VERTEX_CACHE_NUM
| Bits
|
Description
|
| 0-7
|
unsigned, Number of entries in the post-vertex cache (usually 0x4 or 0x84)
|
GPUREG_DRAWARRAYS
| Bits
|
Description
|
| 0-31
|
unsigned, Trigger (0 = idle, non-zero = draw arrays)
|
GPUREG_DRAWELEMENTS
| Bits
|
Description
|
| 0-31
|
unsigned, Trigger (0 = idle, non-zero = draw elements)
|
GPUREG_VTX_FUNC
| Bits
|
Description
|
| 0-31
|
unsigned, Trigger (0 = idle, non-zero = clear post-vertex cache)
|
GPUREG_FIXEDATTRIB_INDEX
| Bits
|
Description
|
| 0-3
|
unsigned, Fixed attribute index (0-11, 0xF = immediate-mode submission)
|
See GPU/Fixed Vertex Attributes and GPU/Immediate-Mode Vertex Submission for usage info.
GPUREG_FIXEDATTRIB_DATA0
| Bits
|
Description
|
| 0-23
|
float1.7.16, Vertex attribute element 1
|
| 24-31
|
float1.7.16, Vertex attribute element 2 (lower 8 bits)
|
Accepts the first part of the four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.
GPUREG_FIXEDATTRIB_DATA1
| Bits
|
Description
|
| 0-23
|
float1.7.16, Vertex attribute element 2 (upper 16 bits)
|
| 24-31
|
float1.7.16, Vertex attribute element 3 (lower 16 bits)
|
Accepts the second part of the four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.
GPUREG_FIXEDATTRIB_DATA2
| Bits
|
Description
|
| 0-23
|
float1.7.16, Vertex attribute element 3 (upper 8 bits)
|
| 24-31
|
float1.7.16, Vertex attribute element 4
|
Accepts the third part of the four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.
GPUREG_CMDBUF_SIZE0
| Bits
|
Description
|
| 0-20
|
unsigned, Size of command buffer 0 >> 3
|
GPUREG_CMDBUF_SIZE1
| Bits
|
Description
|
| 0-20
|
unsigned, Size of command buffer 1 >> 3
|
GPUREG_CMDBUF_ADDR0
| Bits
|
Description
|
| 0-28
|
unsigned, Physical address of command buffer 0 >> 3
|
GPUREG_CMDBUF_ADDR1
| Bits
|
Description
|
| 0-28
|
unsigned, Physical address of command buffer 1 >> 3
|
GPUREG_CMDBUF_JUMP0
| Bits
|
Description
|
| 0-31
|
unsigned, Trigger (0 = idle, non-zero = execute command buffer 0)
|
GPUREG_CMDBUF_JUMP1
| Bits
|
Description
|
| 0-31
|
unsigned, Trigger (0 = idle, non-zero = execute command buffer 1)
|
GPUREG_VSH_NUM_ATTR
| Bits
|
Description
|
| 0-3
|
unsigned, Number of vertex shader input attributes - 1
|
GPUREG_VSH_COM_MODE
| Bits
|
Description
|
| 0
|
unsigned, Geometry shader configuration enabled (0 = disabled, 1 = enabled)
|
| 8-31
|
0x0
|
GPUREG_START_DRAW_FUNC0
| Bits
|
Description
|
| 0
|
unsigned, Mode (0 = drawing, 1 = configuration)
|
| 1-31
|
0x0
|
When the mode value is set to 1, rendering is not performed properly. When set to 0, changes to the vertex shader configuration registers are not applied correctly.
GPUREG_VSH_OUTMAP_TOTAL1
| Bits
|
Description
|
| 0-3
|
unsigned, Number of vertex shader output map registers - 1
|
GPUREG_VSH_OUTMAP_TOTAL2
| Bits
|
Description
|
| 0-3
|
unsigned, Number of vertex shader output map registers - 1
|
GPUREG_GSH_MISC0
| Bits
|
Description
|
| 0-31
|
unsigned, Misc data (0x00000001 = Reserved geometry shader subdivision in use, 0x01004302 = Particle system in use, 0 otherwise)
|
GPUREG_GEOSTAGE_CONFIG2
| Bits
|
Description
|
| 0
|
unsigned, Draw command active (0 = not active, 1 = active)
|
| 8
|
unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|
| 9
|
0x0
|
| 16-31
|
0x0
|
This register is set to 1 before draw arrays/elements calls and cleared immediately after. While set to 1, some register writes out side of the 0x200-0x254 and
0x280-0x2DF ranges may be processed incorrectly.
GPUREG_GSH_MISC1
| Bits
|
Description
|
| 0-4
|
unsigned, Reserved geometry shader subdivision type (2 = Loop, 3 = Catmull-Clark)
|
GPUREG_PRIMITIVE_CONFIG
| Bits
|
Description
|
| 0-3
|
unsigned, Number of vertex shader output map registers - 1
|
| 8-9
|
unsigned, Primitive mode
|
| 16
|
0x0
|
Primitive mode value:
| Value
|
Description
|
| 0
|
Triangles
|
| 1
|
Triangle strip
|
| 2
|
Triangle fan
|
| 3
|
Geometry primitive
|
GPUREG_RESTART_PRIMITIVE
| Bits
|
Description
|
| 0
|
unsigned, Trigger (0 = idle, 1 = reset primitive)
|
| 1-31
|
0x0
|
Shader registers
GPUREG_SH_BOOLUNIFORM
| Bits
|
Description
|
| 0
|
unsigned, Boolean register b0 value (0 = false, 1 = true)
|
| 1
|
unsigned, Boolean register b1 value (0 = false, 1 = true)
|
| 2
|
unsigned, Boolean register b2 value (0 = false, 1 = true)
|
| 3
|
unsigned, Boolean register b3 value (0 = false, 1 = true)
|
| 4
|
unsigned, Boolean register b4 value (0 = false, 1 = true)
|
| 5
|
unsigned, Boolean register b5 value (0 = false, 1 = true)
|
| 6
|
unsigned, Boolean register b6 value (0 = false, 1 = true)
|
| 7
|
unsigned, Boolean register b7 value (0 = false, 1 = true)
|
| 8
|
unsigned, Boolean register b8 value (0 = false, 1 = true)
|
| 9
|
unsigned, Boolean register b9 value (0 = false, 1 = true)
|
| 10
|
unsigned, Boolean register b10 value (0 = false, 1 = true)
|
| 11
|
unsigned, Boolean register b11 value (0 = false, 1 = true)
|
| 12
|
unsigned, Boolean register b12 value (0 = false, 1 = true)
|
| 13
|
unsigned, Boolean register b13 value (0 = false, 1 = true)
|
| 14
|
unsigned, Boolean register b14 value (0 = false, 1 = true)
|
| 15
|
unsigned, Boolean register b15 value (0 = false, 1 = true)
|
| 16-31
|
0x7FFF
|
This register is used to set a shader unit's boolean registers.
GPUREG_SH_INTUNIFORM_Ii
| Bits
|
Description
|
| 0-7
|
unsigned, Integer register ii X value
|
| 8-15
|
unsigned, Integer register ii Y value
|
| 16-23
|
unsigned, Integer register ii Z value
|
| 24-31
|
unsigned, Integer register ii W value
|
These registers are used to set a shader unit's integer registers.
GPUREG_SH_INPUTBUFFER_CONFIG
| Bits
|
Description
|
| 0-3
|
unsigned, Input vertex attributes - 1
|
| 8-15
|
unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use) (always 0 for vertex shaders)
|
| 16-23
|
0x0
|
| 24-31
|
unsigned, Use geometry shader (0x8 = use, 0xA0 = don't use) (always 0xA0 for vertex shaders)
|
This register is used to configure a shader unit's input buffer.
GPUREG_SH_ENTRYPOINT
| Bits
|
Description
|
| 0-15
|
unsigned, Code entry point offset, in 32-bit words
|
| 16-31
|
0x7FFF
|
This register sets a shader unit's code entry point.
For geometry shaders, this sets the entry point for the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entry point, it can also be used to set this single shader unit to run from a different entry point than the other three, even when running a vertex shader.
For vertex shaders, this sets the entry point for the shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.
GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW
| Bits
|
Description
|
| 0-3
|
unsigned, Vertex attribute 0 input register index
|
| 4-7
|
unsigned, Vertex attribute 1 input register index
|
| 8-11
|
unsigned, Vertex attribute 2 input register index
|
| 12-15
|
unsigned, Vertex attribute 3 input register index
|
| 16-19
|
unsigned, Vertex attribute 4 input register index
|
| 20-23
|
unsigned, Vertex attribute 5 input register index
|
| 24-27
|
unsigned, Vertex attribute 6 input register index
|
| 28-31
|
unsigned, Vertex attribute 7 input register index
|
This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 1st attribute.
GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH
| Bits
|
Description
|
| 0-3
|
unsigned, Vertex attribute 8 input register index
|
| 4-7
|
unsigned, Vertex attribute 9 input register index
|
| 8-11
|
unsigned, Vertex attribute 10 input register index
|
| 12-15
|
unsigned, Vertex attribute 11 input register index
|
| 16-19
|
unsigned, Vertex attribute 12 input register index
|
| 20-23
|
unsigned, Vertex attribute 13 input register index
|
| 24-27
|
unsigned, Vertex attribute 14 input register index
|
| 28-31
|
unsigned, Vertex attribute 15 input register index
|
This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 9th attribute.
GPUREG_SH_OUTMAP_MASK
| Bits
|
Description
|
| 0
|
unsigned, Output register o0 enabled (0 = disabled, 1 = enabled)
|
| 1
|
unsigned, Output register o1 enabled (0 = disabled, 1 = enabled)
|
| 2
|
unsigned, Output register o2 enabled (0 = disabled, 1 = enabled)
|
| 3
|
unsigned, Output register o3 enabled (0 = disabled, 1 = enabled)
|
| 4
|
unsigned, Output register o4 enabled (0 = disabled, 1 = enabled)
|
| 5
|
unsigned, Output register o5 enabled (0 = disabled, 1 = enabled)
|
| 6
|
unsigned, Output register o6 enabled (0 = disabled, 1 = enabled)
|
| 7
|
unsigned, Output register o7 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|
| 8
|
unsigned, Output register o8 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|
| 9
|
unsigned, Output register o9 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|
| 10
|
unsigned, Output register o10 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|
| 11
|
unsigned, Output register o11 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|
| 12
|
unsigned, Output register o12 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|
| 13
|
unsigned, Output register o13 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|
| 14
|
unsigned, Output register o14 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|
| 15
|
unsigned, Output register o15 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|
| 16-31
|
0x0
|
This register toggles a shader unit's output registers.
GPUREG_SH_CODETRANSFER_END
| Bits
|
Description
|
| 0-31
|
unsigned, Signal transfer end (0 = idle, non-zero = signal)
|
This register's value should be set to 1 in order to finalize the transfer of shader code.
GPUREG_SH_FLOATUNIFORM_INDEX
| Bits
|
Description
|
| 0-7
|
unsigned, Target floating-point register index (range 0-95, where 0 = c0 and 95 = c95)
|
| 31
|
unsigned, Transfer mode (0 = float1.7.16, 1 = float1.8.23)
|
This register sets the shader unit's target floating-point register and transfer mode for the data transfer system. As such it is typically used right before GPUREG_SH_FLOATUNIFORM_DATAi, though writing to one register does not make writing to the other mandatory.
GPUREG_SH_FLOATUNIFORM_DATAi
| Bits
|
Description
|
| 0-31
|
Floating-point register component data
|
This register is used to set the components of a shader unit's floating-point registers, each having 4 components. The data format which should be written to it depends on the transfer mode set with GPUREG_SH_FLOATUNIFORM_INDEX. This register functions as a FIFO queue: after each time a 4-component uniform register is successfully set, the target register index is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to GPUREG_SH_FLOATUNIFORM_INDEX.
- In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes:
- first word : ZZWWWWWW
- second word : YYYYZZZZ
- third word : XXXXXXYY
- In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.
GPUREG_SH_CODETRANSFER_INDEX
| Bits
|
Description
|
| 0-11
|
unsigned, Target shader code offset
|
This register is used to set the offset at which upcoming shader code data transferred through GPUREG_SH_CODETRANSFER_DATAi should be written.
GPUREG_SH_CODETRANSFER_DATAi
| Bits
|
Description
|
| 0-31
|
unsigned, Shader instruction data
|
This register is used to transfer shader code data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader code memory bank at the offset initially set by GPUREG_SH_CODETRANSFER_INDEX. The offset in question is incremented after each write to this register.
GPUREG_SH_OPDESCS_INDEX
| Bits
|
Description
|
| 0-11
|
unsigned, Target shader operand descriptor offset
|
This register is used to set the offset at which upcoming shader operand descriptor data transferred through GPUREG_SH_OPDESCS_DATAi should be written.
GPUREG_SH_OPDESCS_DATAi
| Bits
|
Description
|
| 0-31
|
unsigned, Shader operand descriptor data
|
This register is used to transfer shader operand descriptor data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader operand descriptor memory bank at the offset initially set by GPUREG_SH_OPDESCS_INDEX. The offset in question is incremented after each write to this register.