GPU/Internal Registers
(this page is hugely WIP)
Overview
GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.
Types
There are three main types of registers :
- configuration registers, which directly map to various rendering properties (for example : GPUREG_FACECULLING_CONFIG)
- data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example : GPUREG_GSH_CODETRANSFER_DATA)
- action triggering registers, which tell the GPU to do something, like draw a primitive (for example : GPUREG_DRAWARRAYS)
Aliases
It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU Commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to GPUREG_VSH_FLOATUNIFORM_DATA so that a consecutively writing command based at 02C0 will write its first parameter to GPUREG_VSH_FLOATUNIFORM_CONFIG and ever subsequent ones to GPUREG_VSH_FLOATUNIFORM_DATA
Register list
GPUREG_FINALIZE
Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software. Failure to write to this register in any command buffer will result in the GPU hanging.
GPUREG_DEPTHBUFFER_FORMAT
The format the current depth buffer should be written into. Following values are possible:
| Value | Description |
|---|---|
| 0 | 16-bit depth |
| 1 | ?? seems to freeze the GPU |
| 2 | 24-bit depth |
| 3 | 24-bit depth + 8-bit stencil (stencil is within bit 24-31) |
GPUREG_COLORBUFFER_FORMAT
Describes the format of the current color buffer used for 3D rendering.
| Bits | Description |
|---|---|
| 0-7 | Pixel size (0=16-bit, 1=24-bit, 2=32-bit, 3=64-bit?) |
| 16-23 | Framebuffer Format (0=GL_RGBA8, 1=GL_RGB8, 2=GL_RGB5_A1, 3=GL_R5_G6_B5, 4=GL_RGBA4).
Note that these values are slightly different from those in GPU#Framebuffer_color_formats. Color components are laid out in reverse byte order, with the most significant bits used first. |
GPUREG_GEOSTAGE_CONFIG
| Bits | Description |
|---|---|
| 0-7 | Geometry stage mode. (0=Vertex shader only, 2=Vertex shader + geometry shader) |
| 0-7 | Unknown. Often set to 1. |
| 0-7 | Unknown. |
| 0-7 | Unknown. Often set to 0. |
This register configures the geometry stage of the GPU pipeline.
Geometry shader registers
GPUREG_GSH_BOOLUNIFORM
| Bits | Description |
|---|---|
| 0 | Value of geometry shader unit's b0 boolean register. (0=true, 1=false) |
| 1 | Value of geometry shader unit's b1 boolean register. (0=true, 1=false) |
| 2 | Value of geometry shader unit's b2 boolean register. (0=true, 1=false) |
| 3 | Value of geometry shader unit's b3 boolean register. (0=true, 1=false) |
| 4 | Value of geometry shader unit's b4 boolean register. (0=true, 1=false) |
| 5 | Value of geometry shader unit's b5 boolean register. (0=true, 1=false) |
| 6 | Value of geometry shader unit's b6 boolean register. (0=true, 1=false) |
| 7 | Value of geometry shader unit's b7 boolean register. (0=true, 1=false) |
| 8 | Value of geometry shader unit's b8 boolean register. (0=true, 1=false) |
| 9 | Value of geometry shader unit's b9 boolean register. (0=true, 1=false) |
| 10 | Value of geometry shader unit's b10 boolean register. (0=true, 1=false) |
| 11 | Value of geometry shader unit's b11 boolean register. (0=true, 1=false) |
| 12 | Value of geometry shader unit's b12 boolean register. (0=true, 1=false) |
| 13 | Value of geometry shader unit's b13 boolean register. (0=true, 1=false) |
| 14 | Value of geometry shader unit's b14 boolean register. (0=true, 1=false) |
| 15 | Value of geometry shader unit's b15 boolean register. (0=true, 1=false) |
| 16-31 | Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang |
This register is used to set the geometry shader unit's boolean registers.
GPUREG_GSH_INTUNIFORM_I0
| Bits | Description |
|---|---|
| 0-7 | Value for geometry shader's i0.x (u8, 0-255) |
| 8-15 | Value for geometry shader's i0.y (u8, 0-255) |
| 16-23 | Value for geometry shader's i0.z (u8, 0-255) |
| 24-31 | Value for geometry shader's i0.w (u8, 0-255) |
This register is used to set the geometry shader's i0 integer register.
GPUREG_GSH_INTUNIFORM_I1
| Bits | Description |
|---|---|
| 0-7 | Value for geometry shader's i1.x (u8, 0-255) |
| 8-15 | Value for geometry shader's i1.y (u8, 0-255) |
| 16-23 | Value for geometry shader's i1.z (u8, 0-255) |
| 24-31 | Value for geometry shader's i1.w (u8, 0-255) |
This register is used to set the geometry shader's i1 integer register.
GPUREG_GSH_INTUNIFORM_I2
| Bits | Description |
|---|---|
| 0-7 | Value for geometry shader's i2.x (u8, 0-255) |
| 8-15 | Value for geometry shader's i2.y (u8, 0-255) |
| 16-23 | Value for geometry shader's i2.z (u8, 0-255) |
| 24-31 | Value for geometry shader's i2.w (u8, 0-255) |
This register is used to set the geometry shader's i2 integer register.
GPUREG_GSH_INTUNIFORM_I3
| Bits | Description |
|---|---|
| 0-7 | Value for geometry shader's i3.x (u8, 0-255) |
| 8-15 | Value for geometry shader's i3.y (u8, 0-255) |
| 16-23 | Value for geometry shader's i3.z (u8, 0-255) |
| 24-31 | Value for geometry shader's i3.w (u8, 0-255) |
This register is used to set the geometry shader's i3 integer register.
GPUREG_GSH_INPUTBUFFER_CONFIG
| Bits | Description |
|---|---|
| 0-7 | Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register) |
| 8-23 | Unknown. These bits typically aren't updated by games. |
| 24-31 | Unknown. This is typically set to 8 for geometry shaders. |
This register is used to configure the geometry shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the input primitive size in registers, though it is not a limit on the number of input registers which can be accessed from the geometry shader.
GPUREG_GSH_ENTRYPOINT
| Bits | Description |
|---|---|
| 0-15 | Geometry shader unit entrypoint, in words. |
| 16-31 | Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang |
This sets the entrypoint for the program running on the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entrypoint, it can also be used to set this single shader unit to run from a different entrypoint than the other three even when running a vertex shader.
GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW
| Bits | Description |
|---|---|
| 0-3 | Index of geometry shader input register which the 1st attribute will be stored in. |
| 4-7 | Index of geometry shader input register which the 2nd attribute will be stored in. |
| 8-11 | Index of geometry shader input register which the 3rd attribute will be stored in. |
| 12-15 | Index of geometry shader input register which the 4th attribute will be stored in. |
| 16-19 | Index of geometry shader input register which the 5th attribute will be stored in. |
| 20-23 | Index of geometry shader input register which the 6th attribute will be stored in. |
| 24-27 | Index of geometry shader input register which the 7th attribute will be stored in. |
| 28-31 | Index of geometry shader input register which the 8th attribute will be stored in. |
This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 1st attribute.
GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH
| Bits | Description |
|---|---|
| 0-3 | Index of geometry shader input register which the 9th attribute will be stored in. |
| 4-7 | Index of geometry shader input register which the 10th attribute will be stored in. |
| 8-11 | Index of geometry shader input register which the 11th attribute will be stored in. |
| 12-15 | Index of geometry shader input register which the 12th attribute will be stored in. |
| 16-19 | Index of geometry shader input register which the 13th attribute will be stored in. |
| 20-23 | Index of geometry shader input register which the 14th attribute will be stored in. |
| 24-27 | Index of geometry shader input register which the 15th attribute will be stored in. |
| 28-31 | Index of geometry shader input register which the 16th attribute will be stored in. |
This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 9th attribute.
GPUREG_GSH_OUTMAP_MASK
| Bits | Description |
|---|---|
| 0 | Enable bit for geometry shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled) |
| 1 | Enable bit for geometry shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled) |
| 2 | Enable bit for geometry shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled) |
| 3 | Enable bit for geometry shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled) |
| 4 | Enable bit for geometry shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled) |
| 5 | Enable bit for geometry shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled) |
| 6 | Enable bit for geometry shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled) |
This register toggles the geometry shader unit's output registers.
GPUREG_GSH_CODETRANSFER_END
| Bits | Description |
|---|---|
| 0 | Code data transfer end signal bit. |
This register's value should be set to 1 in order to finalize the transfer of geometry shader code. It is unknown whether this register is used for other functions.
GPUREG_GSH_FLOATUNIFORM_CONFIG
| Bits | Description |
|---|---|
| 0-6 | Target float vec4 geometry shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95) |
| 31 | Float vec4 geometry shader uniform data transfer mode. (0 = float24, 1 = float32) |
This register sets the target float vec4 geometry shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before GPUREG_GSH_FLOATUNIFORM_DATA, though writing to one register does not make writing to the other mandatory.
GPUREG_GSH_FLOATUNIFORM_DATA
| Bits | Description |
|---|---|
| 0-31 | Float vec4 geometry shader uniform data. (format depends on transfer mode, see below for details) |
This register is used to set the value of float vec4 geometry shader uniform registers. The data format which should be written to it depends on the transfer mode set with GPUREG_GSH_FLOATUNIFORM_CONFIG. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to GPUREG_GSH_FLOATUNIFORM_CONFIG.
- In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
- first word : ZZWWWWWW
- second word : YYYYZZZZ
- third word : XXXXXXYY
- In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.
GPUREG_GSH_CODETRANSFER_CONFIG
| Bits | Description |
|---|---|
| 0-11 | Target geometry shader code offset for data transfer. |
This register is used to set the offset at which upcoming geometry shader code data transferred through GPUREG_GSH_CODETRANSFER_DATA should be written.
NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The shader control flow instructions only have room to address 12 bits though, so it's likely that the maximum is 4095.
GPUREG_GSH_CODETRANSFER_DATA
| Bits | Description |
|---|---|
| 0-31 | Geometry shader instruction data. |
This register is used to transfer geometry shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader code memory bank at the offset initially set by GPUREG_GSH_CODETRANSFER_CONFIG. The offset in question is incremented after each write to this register.
GPUREG_GSH_OPDESCS_CONFIG
| Bits | Description |
|---|---|
| 0-6 | Target geometry shader operand descriptor offset for data transfer. |
This register is used to set the offset at which upcoming geometry shader operand descriptor data transferred through GPUREG_GSH_OPDESCS_DATA should be written.
GPUREG_GSH_OPDESCS_DATA
| Bits | Description |
|---|---|
| 0-31 | Geometry shader operand descriptor data. |
This register is used to transfer geometry shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader operand descriptor memory bank at the offset initially set by GPUREG_GSH_OPDESCS_CONFIG. The offset in question is incremented after each write to this register.
Vertex shader registers
GPUREG_VSH_BOOLUNIFORM
| Bits | Description |
|---|---|
| 0 | Value of vertex shader unit's b0 boolean register. (0=true, 1=false) |
| 1 | Value of vertex shader unit's b1 boolean register. (0=true, 1=false) |
| 2 | Value of vertex shader unit's b2 boolean register. (0=true, 1=false) |
| 3 | Value of vertex shader unit's b3 boolean register. (0=true, 1=false) |
| 4 | Value of vertex shader unit's b4 boolean register. (0=true, 1=false) |
| 5 | Value of vertex shader unit's b5 boolean register. (0=true, 1=false) |
| 6 | Value of vertex shader unit's b6 boolean register. (0=true, 1=false) |
| 7 | Value of vertex shader unit's b7 boolean register. (0=true, 1=false) |
| 8 | Value of vertex shader unit's b8 boolean register. (0=true, 1=false) |
| 9 | Value of vertex shader unit's b9 boolean register. (0=true, 1=false) |
| 10 | Value of vertex shader unit's b10 boolean register. (0=true, 1=false) |
| 11 | Value of vertex shader unit's b11 boolean register. (0=true, 1=false) |
| 12 | Value of vertex shader unit's b12 boolean register. (0=true, 1=false) |
| 13 | Value of vertex shader unit's b13 boolean register. (0=true, 1=false) |
| 14 | Value of vertex shader unit's b14 boolean register. (0=true, 1=false) |
| 15 | Value of vertex shader unit's b15 boolean register. (0=true, 1=false) |
| 16-31 | Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang |
This register is used to set the vertex shader unit's boolean registers.
GPUREG_VSH_INTUNIFORM_I0
| Bits | Description |
|---|---|
| 0-7 | Value for vertex shader's i0.x (u8, 0-255) |
| 8-15 | Value for vertex shader's i0.y (u8, 0-255) |
| 16-23 | Value for vertex shader's i0.z (u8, 0-255) |
| 24-31 | Value for vertex shader's i0.w (u8, 0-255) |
This register is used to set the vertex shader's i0 integer register.
GPUREG_VSH_INTUNIFORM_I1
| Bits | Description |
|---|---|
| 0-7 | Value for vertex shader's i1.x (u8, 0-255) |
| 8-15 | Value for vertex shader's i1.y (u8, 0-255) |
| 16-23 | Value for vertex shader's i1.z (u8, 0-255) |
| 24-31 | Value for vertex shader's i1.w (u8, 0-255) |
This register is used to set the vertex shader's i1 integer register.
GPUREG_VSH_INTUNIFORM_I2
| Bits | Description |
|---|---|
| 0-7 | Value for vertex shader's i2.x (u8, 0-255) |
| 8-15 | Value for vertex shader's i2.y (u8, 0-255) |
| 16-23 | Value for vertex shader's i2.z (u8, 0-255) |
| 24-31 | Value for vertex shader's i2.w (u8, 0-255) |
This register is used to set the vertex shader's i2 integer register.
GPUREG_VSH_INTUNIFORM_I3
| Bits | Description |
|---|---|
| 0-7 | Value for vertex shader's i3.x (u8, 0-255) |
| 8-15 | Value for vertex shader's i3.y (u8, 0-255) |
| 16-23 | Value for vertex shader's i3.z (u8, 0-255) |
| 24-31 | Value for vertex shader's i3.w (u8, 0-255) |
This register is used to set the vertex shader's i3 integer register.
GPUREG_VSH_INPUTBUFFER_CONFIG
| Bits | Description |
|---|---|
| 0-7 | Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register) |
| 8-23 | Unknown. These bits typically aren't updated by games. |
| 24-31 | Unknown. This is typically set to 0xA for vertex shaders. |
This register is used to configure the vertex shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the number of attributes per vertex.
GPUREG_VSH_ENTRYPOINT
| Bits | Description |
|---|---|
| 0-15 | Vertex shader entrypoint, in words. |
| 16-31 | Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang |
This sets the entrypoint for the program running on shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.
GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW
| Bits | Description |
|---|---|
| 0-3 | Index of vertex shader input register which the 1st attribute will be stored in. |
| 4-7 | Index of vertex shader input register which the 2nd attribute will be stored in. |
| 8-11 | Index of vertex shader input register which the 3rd attribute will be stored in. |
| 12-15 | Index of vertex shader input register which the 4th attribute will be stored in. |
| 16-19 | Index of vertex shader input register which the 5th attribute will be stored in. |
| 20-23 | Index of vertex shader input register which the 6th attribute will be stored in. |
| 24-27 | Index of vertex shader input register which the 7th attribute will be stored in. |
| 28-31 | Index of vertex shader input register which the 8th attribute will be stored in. |
This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 1st attribute.
GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH
| Bits | Description |
|---|---|
| 0-3 | Index of vertex shader input register which the 9th attribute will be stored in. |
| 4-7 | Index of vertex shader input register which the 10th attribute will be stored in. |
| 8-11 | Index of vertex shader input register which the 11th attribute will be stored in. |
| 12-15 | Index of vertex shader input register which the 12th attribute will be stored in. |
| 16-19 | Index of vertex shader input register which the 13th attribute will be stored in. |
| 20-23 | Index of vertex shader input register which the 14th attribute will be stored in. |
| 24-27 | Index of vertex shader input register which the 15th attribute will be stored in. |
| 28-31 | Index of vertex shader input register which the 16th attribute will be stored in. |
This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 9th attribute.
GPUREG_VSH_OUTMAP_MASK
| Bits | Description |
|---|---|
| 0 | Enable bit for vertex shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled) |
| 1 | Enable bit for vertex shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled) |
| 2 | Enable bit for vertex shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled) |
| 3 | Enable bit for vertex shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled) |
| 4 | Enable bit for vertex shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled) |
| 5 | Enable bit for vertex shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled) |
| 6 | Enable bit for vertex shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled) |
| 7 | Enable bit for vertex shader's o7 output register. (1 = o7 enabled, 0 = o7 disabled) |
| 8 | Enable bit for vertex shader's o8 output register. (1 = o8 enabled, 0 = o8 disabled) |
| 9 | Enable bit for vertex shader's o9 output register. (1 = o9 enabled, 0 = o9 disabled) |
| 10 | Enable bit for vertex shader's o10 output register. (1 = o10 enabled, 0 = o10 disabled) |
| 11 | Enable bit for vertex shader's o11 output register. (1 = o11 enabled, 0 = o11 disabled) |
| 12 | Enable bit for vertex shader's o12 output register. (1 = o12 enabled, 0 = o12 disabled) |
| 13 | Enable bit for vertex shader's o13 output register. (1 = o13 enabled, 0 = o13 disabled) |
| 14 | Enable bit for vertex shader's o14 output register. (1 = o14 enabled, 0 = o14 disabled) |
| 15 | Enable bit for vertex shader's o15 output register. (1 = o15 enabled, 0 = o15 disabled) |
This register toggles the vertex shader units' output registers.
GPUREG_VSH_CODETRANSFER_END
| Bits | Description |
|---|---|
| 0 | Code data transfer end signal bit. |
This register's value should be set to 1 in order to finalize the transfer of vertex shader code. It is unknown whether this register is used for other functions.
GPUREG_VSH_FLOATUNIFORM_CONFIG
| Bits | Description |
|---|---|
| 0-6 | Target float vec4 vertex shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95) |
| 31 | Float vec4 vertex shader uniform data transfer mode. (0 = float24, 1 = float32) |
This register sets the target float vec4 vertex shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before GPUREG_VSH_FLOATUNIFORM_DATA, though writing to one register does not make writing to the other mandatory.
GPUREG_VSH_FLOATUNIFORM_DATA
| Bits | Description |
|---|---|
| 0-31 | Float vec4 vertex shader uniform data. (format depends on transfer mode, see below for details) |
This register is used to set the value of float vec4 vertex shader uniform registers. The data format which should be written to it depends on the transfer mode set with GPUREG_VSH_FLOATUNIFORM_CONFIG. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to GPUREG_VSH_FLOATUNIFORM_CONFIG.
- In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
- first word : ZZWWWWWW
- second word : YYYYZZZZ
- third word : XXXXXXYY
- In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.
GPUREG_VSH_CODETRANSFER_CONFIG
| Bits | Description |
|---|---|
| 0-11 | Target vertex shader code offset for data transfer. |
This register is used to set the offset at which upcoming vertex shader code data transferred through GPUREG_VSH_CODETRANSFER_DATA should be written.
NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The shader control flow instructions only have room to address 12 bits though, so it's likely that the maximum is 4095.
GPUREG_VSH_CODETRANSFER_DATA
| Bits | Description |
|---|---|
| 0-31 | Vertex shader instruction data. |
This register is used to transfer vertex shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader code memory bank at the offset initially set by GPUREG_VSH_CODETRANSFER_CONFIG. The offset in question is incremented after each write to this register.
GPUREG_VSH_OPDESCS_CONFIG
| Bits | Description |
|---|---|
| 0-6 | Target vertex shader operand descriptor offset for data transfer. |
This register is used to set the offset at which upcoming vertex shader operand descriptor data transferred through GPUREG_VSH_OPDESCS_DATA should be written.
GPUREG_VSH_OPDESCS_DATA
| Bits | Description |
|---|---|
| 0-31 | Vertex shader operand descriptor data. |
This register is used to transfer vertex shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader operand descriptor memory bank at the offset initially set by GPUREG_VSH_OPDESCS_CONFIG. The offset in question is incremented after each write to this register.