Difference between revisions of "I2C Registers"
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| Line 317: | Line 317: | ||
| 0x2 | | 0x2 | ||
| 0x1 | | 0x1 | ||
| − | | FCR | + | | FCR/IIR |
|- | |- | ||
| 0x18 | | 0x18 | ||
| Line 323: | Line 323: | ||
| 0x1 | | 0x1 | ||
| LCR | | LCR | ||
| + | |- | ||
| + | | 0x20 | ||
| + | | 0x4 | ||
| + | | 0x1 | ||
| + | | MCR | ||
| + | |- | ||
| + | | 0x28 | ||
| + | | 0x5 | ||
| + | | 0x1 | ||
| + | | LSR | ||
| + | |- | ||
| + | | 0x30 | ||
| + | | 0x6 | ||
| + | | 0x1 | ||
| + | | MSR/TCR | ||
| + | |- | ||
| + | | 0x38 | ||
| + | | 0x7 | ||
| + | | 0x1 | ||
| + | | SPR/TLR | ||
| + | |- | ||
| + | | 0x40 | ||
| + | | 0x8 | ||
| + | | 0x1 | ||
| + | | TXLVL | ||
|- | |- | ||
| 0x48 | | 0x48 | ||
| Line 328: | Line 353: | ||
| 0x1 | | 0x1 | ||
| RXLVL | | RXLVL | ||
| + | |- | ||
| + | | 0x50 | ||
| + | | 0xA | ||
| + | | 0x1 | ||
| + | | IODir | ||
|- | |- | ||
| 0x58 | | 0x58 | ||
| Line 333: | Line 363: | ||
| 0x1 | | 0x1 | ||
| IOState | | IOState | ||
| + | |- | ||
| + | | 0x60 | ||
| + | | 0xC | ||
| + | | 0x1 | ||
| + | | IoIntEna | ||
| + | |- | ||
| + | | 0x68 | ||
| + | | 0xD | ||
| + | | 0x1 | ||
| + | | reserved | ||
| + | |- | ||
| + | | 0x70 | ||
| + | | 0xE | ||
| + | | 0x1 | ||
| + | | IOControl | ||
|- | |- | ||
| 0x78 | | 0x78 | ||
Revision as of 07:15, 25 July 2014
Registers
| NAME | PHYSICAL ADDRESS | PROCESS ADDRESS | WIDTH |
|---|---|---|---|
| REG_I2C1DATA | 0x10161000 | 0x1EC61000 | 1 |
| REG_I2C1CNT | 0x10161001 | 0x1EC61001 | 1 |
| REG_I2C1CNTEX | 0x10161002 | 0x1EC61002 | 2 |
| REG_I2C1SCL | 0x10161004 | 0x1EC61004 | 2 |
| REG_I2C2DATA | 0x10144000 | 0x1EC44000 | 1 |
| REG_I2C2CNT | 0x10144001 | 0x1EC44001 | 1 |
| REG_I2C2CNTEX | 0x10144002 | 0x1EC44002 | 2 |
| REG_I2C2SCL | 0x10144004 | 0x1EC44004 | 2 |
| REG_I2C3DATA | 0x10148000 | 0x1EC48000 | 1 |
| REG_I2C3CNT | 0x10148001 | 0x1EC48001 | 1 |
| REG_I2C3CNTEX | 0x10148002 | 0x1EC48002 | 2 |
| REG_I2C3SCL | 0x10148004 | 0x1EC48004 | 2 |
I2C Devices
| Device id | Device bus id | Device address | Device description |
|---|---|---|---|
| 0 | 1 | 0x4a | Power management?(same device addr as the DSi power-management) |
| 1 | 1 | 0x7a | Camera0?(same dev-addr as DSi cam0) |
| 2 | 1 | 0x78 | Camera1?(same dev-addr as DSi cam1) |
| 3 | 2 | 0x4a | MCU |
| 4 | 2 | 0x78 | ? |
| 5 | 2 | 0x2c | ? |
| 6 | 2 | 0x2e | ? |
| 7 | 2 | 0x40 | ? |
| 8 | 2 | 0x44 | ? |
| 9 | 3 | 0xa6 | ? |
| 10 | 3 | 0xd0 | ? |
| 11 | 3 | 0xd2 | ? |
| 12 | 3 | 0xa4 | ? |
| 13 | 3 | 0x9a | IR |
| 14 | 3 | 0xa0 | eeprom? |
Device 3
| REGISTER | WIDTH | DESCRIPTION |
|---|---|---|
| 0x03 | 8 | ? |
| 0x04 | 8 | ? |
| 0x09 | 1 | Sound volume: 0x0..0x3F. |
| 0x18 | 8 | ? |
| 0x20 | 8 | Writing u8 value 4 here triggers a hardware system reboot. Writing u8 value 8 triggers a shutdown via power-off? |
| 0x22 | 8 | ? |
| 0x23 | 8 | ? |
| 0x24 | 8 | ? |
| 0x28 | 8 | ? |
| 0x29 | 8 | ? |
| 0x2A | 8 | ? |
| 0x2B | 8 | ? |
| 0x2C | 8 | ? |
| 0x2D | 0x64 | This is used for controlling the notification LED(see MCURTC:SetInfoLEDPatternHeader as well), when this register is written. |
| 0x2E | 1 | This returns the notification LED status when read. |
| 0x30 | 8 | ? |
| 0x31 | 8 | ? |
| 0x32 | 8 | ? |
| 0x33 | 8 | ? |
| 0x34 | 8 | ? |
| 0x35 | 8 | ? |
| 0x36 | 8 | ? |
| 0x37 | 8 | ? |
| 0x38 | 8 | ? |
| 0x39 | 8 | ? |
| 0x3A | 8 | ? |
| 0x3B | 8 | ? |
| 0x3C | 8 | ? |
| 0x41 | 8 | ? |
| 0x43 | 8 | ? |
| 0x4E | 8 | ? |
| 0x50 | 8 | ? |
| 0x51 | 8 | ? |
| 0x58 | 8 | ? |
| 0x60 | 8 | ? |
Device 13
| Raw I2C register address | Internal register address | Width | Description |
|---|---|---|---|
| 0x0 | 0x0 | 0x40 | RHR / THR (data receive/send FIFO) |
| 0x8 | 0x1 | 0x1 | IER |
| 0x10 | 0x2 | 0x1 | FCR/IIR |
| 0x18 | 0x3 | 0x1 | LCR |
| 0x20 | 0x4 | 0x1 | MCR |
| 0x28 | 0x5 | 0x1 | LSR |
| 0x30 | 0x6 | 0x1 | MSR/TCR |
| 0x38 | 0x7 | 0x1 | SPR/TLR |
| 0x40 | 0x8 | 0x1 | TXLVL |
| 0x48 | 0x9 | 0x1 | RXLVL |
| 0x50 | 0xA | 0x1 | IODir |
| 0x58 | 0xB | 0x1 | IOState |
| 0x60 | 0xC | 0x1 | IoIntEna |
| 0x68 | 0xD | 0x1 | reserved |
| 0x70 | 0xE | 0x1 | IOControl |
| 0x78 | 0xF | 0x1 | EFCR |
See the datasheet linked to on the Hardware page for reference. From that datasheet, for the structure of the I2C register address u8: "Bit 0 is not used, bits 2:1 select the channel, bits 6:3 select one of the UART internal registers. Bit 7 is not used with the I2C-bus interface, but it is used by the SPI interface to indicate a read or a write operation."
I2CCNT
| BIT | DESCRIPTION |
|---|---|
| 0 | HOLD (0=Last byte of transaction, 1=More bytes coming) |
| 2 | Error flag/ack? |
| 4 | Read mode related? |
| 5 | Read mode? |
| 6 | IRQ enable? |
| 7 | Enable? |