Difference between revisions of "GPU/External Registers"
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| Line 118: | Line 118: | ||
|- | |- | ||
| 0 | | 0 | ||
| − | | | + | | When set, the framebuffer data is flipped vertically.(Usually zero) |
|- | |- | ||
| 1 | | 1 | ||
| Line 124: | Line 124: | ||
|- | |- | ||
| 2 | | 2 | ||
| − | | This bit is set when out-framebuf width/height is less than the input framebuf width/height, clear otherwise. Bit24 is normally clear when this bit is set. | + | | This bit is set when the out-framebuf width/height is less than the input framebuf width/height, clear otherwise. Bit24 is normally clear when this bit is set. |
|- | |- | ||
| 4-3 | | 4-3 | ||
Revision as of 18:09, 30 March 2013
Map
Init Values from nngxInitialize for Top Screen
- 0x1EF00400 = 0x1C2
- 0x1EF00404 = 0xD1
- 0x1EF00408 = 0x1C1
- 0x1EF0040C = 0x1C1
- 0x1EF00410 = 0
- 0x1EF00414 = 0xCF
- 0x1EF00418 = 0xD1
- 0x1EF0041C = 0x1C501C1
- 0x1EF00420 = 0x10000
- 0x1EF00424 = 0x19D
- 0x1EF00428 = 2
- 0x1EF0042C = 0x1C2
- 0x1EF00430 = 0x1C2
- 0x1EF00434 = 0x1C2
- 0x1EF00438 = 1
- 0x1EF0043C = 2
- 0x1EF00440 = 0x1960192
- 0x1EF00444 = 0
- 0x1EF00448 = 0
- 0x1EF0045C = 0x19000F0
- 0x1EF00460 = 0x1c100d1
- 0x1EF00464 = 0x1920002
- 0x1EF00470 = 0x80340
- 0x1EF0049C = 0
More Init Values from nngxInitialize for Top Screen
- 0x1EF00468 = 0x18300000, later changed by GSP module when updating state, framebuffer
- 0x1EF0046C = 0x18300000, later changed by GSP module when updating state, framebuffer
- 0x1EF00494 = 0x18300000
- 0x1EF00498 = 0x18300000
- 0x1EF00478 = 1, doesn't stay 1, read as 0
- 0x1EF00474 = 0x10501
0x1EF018E0
| Register address | Description |
|---|---|
| 0x1EF018E0 | Buffer Size>>3 |
| 0x1EF018E8 | Buffer physical address>>3 |
| 0x1EF018F0 | Writing value 1 here triggers GPU processing for the specified buffer |
These 3 registers are used by GX command 1. This is used for GPU commands.
0x1EF00010
| Register address | Description |
|---|---|
| 0x1EF000X0 | Buffer physical address>>3 |
| 0x1EF000X4 | Associated buffer physical address>>3 |
| 0x1EF000X8 | Buffer size |
| 0x1EF000XC | The low u16 for this register is overwritten by the GX command u16 parameter |
These registers are used by GX command 2. 0x1EF00010 is used for the GX command buf0 parameters, while 0x1EF00020 is used for the GX command buf1 parameters.
0x1EF00C00
| Register address | Description |
|---|---|
| 0x1EF00C00 | Input GPU framebuffer physical address>>3 |
| 0x1EF00C04 | Output LCD framebuffer physical address>>3 |
| 0x1EF00C08 | Output framebuffer dimensions, used with cmd3 |
| 0x1EF00C0C | Input framebuffer dimensions, used with cmd3 |
| 0x1EF00C10 | Flags, used with cmd3 and cmd4. |
| 0x1EF00C14 | GSP module writes value 0 here prior to writing to 0x1EF00C18, for cmd3. |
| 0x1EF00C18 | Writing value 1 here triggers GPU processing for the specified buffers. |
| 0x1EF00C20 | Unknown, used with cmd4 |
| 0x1EF00C24 | Unknown, used with cmd4 |
| 0x1EF00C28 | Unknown, used with cmd4 |
These registers are used by GX command 3 and 4. For cmd4, *0x1EF00C18 |= 1 is used instead of just writing value 1. The dimensions fields seem to use the same format as LCD register 0x1EF00X5C. The input framebuffer width for the main screen is normally 480.
0x1EF00C10
| Bit | Description |
|---|---|
| 0 | When set, the framebuffer data is flipped vertically.(Usually zero) |
| 1 | ? |
| 2 | This bit is set when the out-framebuf width/height is less than the input framebuf width/height, clear otherwise. Bit24 is normally clear when this bit is set. |
| 4-3 | Unused |
| 5 | ? |
| 7-6 | Unused |
| 10-8 | Input framebuffer color format, value0 and value1 are the same as the LCD framebuffer formats.(Usually zero) |
| 11 | Unused |
| 14-12 | Output framebuffer color format |
| 15 | Unused |
| 16 | When this is set, the framebuffer data is converted to tiles. |
| 19-17 | Unused |
| 21-20 | Unknown, output framebuffer data doesn't seem to change when this value is changed.(Usually zero) |
| 23-22 | Unused |
| 24 | When this is set, the actual output framebuffer width is width>>1. |
| 31-25 | Unused |