Difference between revisions of "GPU/External Registers"
| Line 36: | Line 36: | ||
* 0x1EF00478 = 1, doesn't stay 1, read as 0 | * 0x1EF00478 = 1, doesn't stay 1, read as 0 | ||
* 0x1EF00474 = 0x10501 | * 0x1EF00474 = 0x10501 | ||
| + | |||
| + | == 0x1EF00X5C == | ||
| + | {| class="wikitable" border="1" | ||
| + | ! Bit | ||
| + | ! Description | ||
| + | |- | ||
| + | | 15-0 | ||
| + | | Framebuffer width? | ||
| + | |- | ||
| + | | 31-16 | ||
| + | | Framebuffer height? | ||
| + | |} | ||
| + | |||
| + | This register might control the framebuffer dimensions, however writing to this doesn't affect the displayed LCD image. | ||
== 0x1EF00X78 == | == 0x1EF00X78 == | ||
| Line 43: | Line 57: | ||
|- | |- | ||
| 0 | | 0 | ||
| − | | | + | | LCD framebuffer to display (0=first, 1=second) |
|- | |- | ||
| 7-1 | | 7-1 | ||
Revision as of 18:35, 29 January 2013
Map
- 0x1EF00400 is the top screen
- 0x1EF00500 is the bottom screen
Init Values from nngxInitialize for Top Screen
- 0x1EF00400 = 0x1C2
- 0x1EF00404 = 0xD1
- 0x1EF00408 = 0x1C1
- 0x1EF0040C = 0x1C1
- 0x1EF00410 = 0
- 0x1EF00414 = 0xCF
- 0x1EF00418 = 0xD1
- 0x1EF0041C = 0x1C501C1
- 0x1EF00420 = 0x10000
- 0x1EF00424 = 0x19D
- 0x1EF00428 = 2
- 0x1EF0042C = 0x1C2
- 0x1EF00430 = 0x1C2
- 0x1EF00434 = 0x1C2
- 0x1EF00438 = 1
- 0x1EF0043C = 2
- 0x1EF00440 = 0x1960192
- 0x1EF00444 = 0
- 0x1EF00448 = 0
- 0x1EF0045C = 0x19000F0
- 0x1EF00460 = 0x1c100d1
- 0x1EF00464 = 0x1920002
- 0x1EF00470 = 0x80340
- 0x1EF0049C = 0
More Init Values from nngxInitialize for Top Screen
- 0x1EF00468 = 0x18300000, later changed by GSP module when updating state, framebuffer
- 0x1EF0046C = 0x18300000, later changed by GSP module when updating state, framebuffer
- 0x1EF00494 = 0x18300000
- 0x1EF00498 = 0x18300000
- 0x1EF00478 = 1, doesn't stay 1, read as 0
- 0x1EF00474 = 0x10501
0x1EF00X5C
| Bit | Description |
|---|---|
| 15-0 | Framebuffer width? |
| 31-16 | Framebuffer height? |
This register might control the framebuffer dimensions, however writing to this doesn't affect the displayed LCD image.
0x1EF00X78
| Bit | Description |
|---|---|
| 0 | LCD framebuffer to display (0=first, 1=second) |
| 7-1 | ? |
| 31-8 | Unused |
0x1EF00X90
| Bit | Description |
|---|---|
| 3-0 | ? |
| 7-4 | Controls the framebuffer dimensions and/or color format |
| 31-7 | ? |
This register controls how the LCD framebuffer is displayed.
Framebuffers
| Address | Description |
|---|---|
| 0x1EF00468 | Main LCD, first framebuffer for 3D left |
| 0x1EF0046C | Main LCD, second framebuffer for 3D left |
| 0x1EF00494 | Main LCD, first framebuffer for 3D right |
| 0x1EF00498 | Main LCD, second framebuffer for 3D right |
| 0x1EF00568 | Sub LCD, first framebuffer |
| 0x1EF0056C | Sub LCD, second framebuffer |
The above framebuffer registers contains the physical address for each framebuffer, normally located in FCRAM in the application's GSP heap.
These LCD framebuffers normally contain the last rendered frames from the GPU. The color format is BGR8. The framebuffers are drawn from left-to-right, instead of top-to-bottom.(Thus the beginning of the framebuffer is drawn starting at the left side of the screen)
Both of the 3D screen left/right framebuffers are displayed regardless of the 3D slider's state, normally when the 3D slider's state is set to "off" the left/right framebuffer addresses are set to the same physical address.