I2C Registers: Difference between revisions
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| 0xa0 | | 0xa0 | ||
| ? | | ? | ||
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= I2CCNT = | |||
{| class="wikitable" border="1" | |||
|+ REG_TMxCNT | |||
! BIT | |||
! DESCRIPTION | |||
|- | |||
| 0 | |||
| HOLD (0=Last byte of transaction, 1=More bytes coming) | |||
|- | |||
| 2 | |||
| Error flag/ack? | |||
|- | |||
| 4 | |||
| Read mode related? | |||
|- | |||
| 5 | |||
| Read mode? | |||
|- | |||
| 6 | |||
| IRQ enable? | |||
|- | |||
| 7 | |||
| Enable? | |||
|} | |} | ||
Revision as of 17:57, 16 December 2012
Registers
| NAME | ADDRESS | WIDTH |
|---|---|---|
| REG_I2C1DATA | 0x1EC16100 | 1 |
| REG_I2C1CNT | 0x1EC16101 | 1 |
| REG_I2C1CNTEX | 0x1EC16102 | 2 |
| REG_I2C1SCL | 0x1EC16104 | 2 |
| REG_I2C2DATA | 0x1EC14400 | 1 |
| REG_I2C2CNT | 0x1EC14401 | 1 |
| REG_I2C2CNTEX | 0x1EC14402 | 2 |
| REG_I2C2SCL | 0x1EC14404 | 2 |
| REG_I2C3DATA | 0x1EC14800 | 1 |
| REG_I2C3CNT | 0x1EC14801 | 1 |
| REG_I2C3CNTEX | 0x1EC14802 | 2 |
| REG_I2C3SCL | 0x1EC14804 | 2 |
I2C Devices
| Device I2C bus | Device address | Device description |
|---|---|---|
| 1 | 0x4a | Power management?(same device addr as the DSi power-management) |
| 1 | 0x7a | Camera0?(same dev-addr as DSi cam0) |
| 1 | 0x78 | Camera1?(same dev-addr as DSi cam1) |
| 2 | 0x4a | ? |
| 2 | 0x78 | ? |
| 2 | 0x2c | ? |
| 2 | 0x2e | ? |
| 2 | 0x40 | ? |
| 2 | 0x44 | ? |
| 3 | 0xa6 | ? |
| 3 | 0xd0 | ? |
| 3 | 0xd2 | ? |
| 3 | 0xa4 | ? |
| 3 | 0x9a | ? |
| 3 | 0xa0 | ? |
I2CCNT
| BIT | DESCRIPTION |
|---|---|
| 0 | HOLD (0=Last byte of transaction, 1=More bytes coming) |
| 2 | Error flag/ack? |
| 4 | Read mode related? |
| 5 | Read mode? |
| 6 | IRQ enable? |
| 7 | Enable? |