Difference between revisions of "Pinouts"

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([WIP] Update MCU info + reformat table + merge TP numbers from page history)
 
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== UC CTR ==
 
== UC CTR ==
  
−
This MCU seems to be a customized 64 pin FLGA version of this: https://www.renesas.com/ko-kr/doc/products/mpumcu/doc/rl78/r01ds0053ej0330-rl78g14.pdf
+
The MCU seems to most closely resemble an NEC (Renesas) 78K0R/Kx3-L 64-pin FBGA: https://www.renesas.com/us/en/document/mah/78k0rkx3-l-users-manual-hardware-r01uh0106ej040078k0rkx3l?language=en&r=1051991
  
−
The pin layouts are similar, but not the same
+
The functional pin mapping is almost exactly the same, except the GPIO port assignment is almost completely different.
 +
 
 +
Most low port numbers appear to map to the correct physical pin locations as described in the above datasheet, however around P7 and above this mapping is definitely altered.
  
 
Orientation: Pin 1 marker in bottom left corner
 
Orientation: Pin 1 marker in bottom left corner
  
−
===Hardware pins===
+
===Pinout===
  
 
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:26%;"
 
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:26%;"
 +
|-
 +
|style="background: #eaecf0" | 8
 
| style="background: #d9ffb3" | + || style="background: #bbbbbb" | G || || || TP75 || style="background: #ffaaaa" | X || style="background: #ffaaaa" | X || style="background: #4d4d33" | ?  
 
| style="background: #d9ffb3" | + || style="background: #bbbbbb" | G || || || TP75 || style="background: #ffaaaa" | X || style="background: #ffaaaa" | X || style="background: #4d4d33" | ?  
 
|-
 
|-
 +
|style="background: #eaecf0" | 7
 
| style="background: #73e600" | SCL || || style="background: #bbbbbb" | G || || /RESET || style="background: #4d4d33" | ? || style="background: #4d4d33" | ? || style="background: #d9ffb3" | +  
 
| style="background: #73e600" | SCL || || style="background: #bbbbbb" | G || || /RESET || style="background: #4d4d33" | ? || style="background: #4d4d33" | ? || style="background: #d9ffb3" | +  
 
|-
 
|-
 +
|style="background: #eaecf0" | 6
 
| style="background: #73e600" | SDA || || style="background: #d9ffb3" | + || TP77 || TP76 || || || style="background: #d9ffb3" | +  
 
| style="background: #73e600" | SDA || || style="background: #d9ffb3" | + || TP77 || TP76 || || || style="background: #d9ffb3" | +  
 
|-
 
|-
 +
|style="background: #eaecf0" | 5
 
| style="background: #4d4d33" | ? || || TP78 || PWRLED1 || || || || CHRGLED
 
| style="background: #4d4d33" | ? || || TP78 || PWRLED1 || || || || CHRGLED
 
|-
 
|-
 +
|style="background: #eaecf0" | 4
 
| || || || || || || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G  
 
| || || || || || || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G  
 
|-
 
|-
 +
|style="background: #eaecf0" | 3
 
| || PWRBTN || || || || || BATTTHM ||
 
| || PWRBTN || || || || || BATTTHM ||
 
|-
 
|-
 +
|style="background: #eaecf0" | 2
 
| || || || PWRLED0 || || || HOMEBTN ||
 
| || || || PWRLED0 || || || HOMEBTN ||
 
|-
 
|-
 +
|style="background: #eaecf0" | 1
 
| style="background: #d9ffb3" | + || || || || style="background: #8efab4" | SCL || style="background: #8efab4" | SDA || || style="background: #bbbbbb" | G  
 
| style="background: #d9ffb3" | + || || || || style="background: #8efab4" | SCL || style="background: #8efab4" | SDA || || style="background: #bbbbbb" | G  
 +
|-
 +
!/
 +
!A
 +
!B
 +
!C
 +
!D
 +
!E
 +
!F
 +
!G
 +
!H
 
|}
 
|}
  
−
===Software pins===
+
===Pin assignment===
 +
 
 +
und = undocumented / custom
 +
SFR = Special Function Register (SFR bank 1, range FFF00h - FFFFFh)
 +
ESR = Extended Special Function Register (SFR bank 2, range F0000h - F0806h)
 +
/  = active low (ground to enable, pull to power supply to disable)
  
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
−
!  Port ID
+
!  TP
−
!  Pin ID
+
!  Pin
 +
!  Port
 
!  Purpose
 
!  Purpose
 
|-
 
|-
−
| 020
+
| TP79
−
| ??
+
| A8
 +
| EVdd
 +
| Digital voltage source input (positive)
 +
|-
 +
| TP74
 +
| E7
 +
| /RESET
 +
| Resets the MCU when grounded, but is also used when reprogramming
 +
|-
 +
| TP75
 +
| E8
 +
| FLMD0
 +
| Flash mode(?) used when reprogramming with external programmer
 +
|-
 +
| TP76
 +
| E6
 +
| TOOL1
 +
| Used when using an ICE or debugger
 +
|-
 +
| TP77
 +
| D6
 +
| TOOL0
 +
| Multipurpose pin for reprogramming and debugging
 +
|-
 +
|
 +
| A7
 +
| SCL0 / P6.0
 +
| DSi-side I2C SCL
 +
|-
 +
|
 +
| A6
 +
| SDA0 / P6.1
 +
| DSi-side I2C SDA
 +
|-
 +
|
 +
| E1
 +
| SCL1 / ESR[510h].und
 +
| 3DS-side SCL
 +
|-
 +
|
 +
| F1
 +
| SDA1 / ESR[510h].und
 +
| 3DS-side SDA
 +
|-
 +
|
 +
| F7
 +
| /P0.1
 +
| SocReset_n (one of the two SoC reset signals)
 +
|-
 +
|
 +
| G7
 +
| /P0.0
 +
| SocReset_n (one of the two SoC reset signals)
 +
|-
 +
|
 +
|
 +
| /P3.0
 +
| Unknown. Probably resets something, as it's poked in a similar pattern to the SoC reset signals.
 +
|-
 +
|
 +
|
 +
| P5.0
 +
| Toggles something (poked in conjunction with reset signals)
 +
|-
 +
|
 +
|
 +
| P2.0
 
| HOME button
 
| HOME button
 
|-
 
|-
−
| 043
+
|  
−
| ??
+
|  
 +
| P4.3
 
| Charging LED(?)
 
| Charging LED(?)
 
|-
 
|-
−
| 051
+
|  
−
| ??
+
|  
 +
| P5.1
 
| Charger "button"
 
| Charger "button"
 
|-
 
|-
−
| 073
+
|  
−
| ??
+
|  
 +
| P7.0
 +
| ???
 +
|-
 +
|
 +
|
 +
| P2.4
 +
| BatteryChargeState (?)
 +
|-
 +
|
 +
|
 +
| P7.3
 
| Power button
 
| Power button
 
|-
 
|-
−
| 074
+
|  
−
| ??
+
|  
 +
| P7.4
 
| WiFi button
 
| WiFi button
 
|-
 
|-
−
| 076
+
|  
−
| ??
+
|  
 +
| P7.6
 
| External IRQ (MCU --> SoC)
 
| External IRQ (MCU --> SoC)
 
|}
 
|}

Latest revision as of 06:35, 24 September 2021

CTR CPU B[edit]

G 0? CS1 ? ? D5 D2 RST CLK G G X X 3v3 3v3 3v3 ? ? ? IRIRQ ? ? G
1? 2? CSx CSy ? D6 D3 D0 IRQ CS1 G G G G 3v3 3v3 G ? ? ? ? ? ?
3? ? ?
3v3 D7 D4 D1 DET CS2 G G G 3v3 3v3 G 3v3 3v3 3v3 ? ? ? ? ? IRTX ? ? ?
CLK D0 G 1v2 3v3 G 1v2 3v3 G 1v2 G G 1v2 3v3 G 1v2 3v3 G 1v2 3v3 G 1v2 3v3 G ? ? ?
D1 D2 D3 3v3 1v2 ? ? ?
CMD IRQ WP 1v2 1v8 ? ? ?
CLK D0 G 3v3 G 3v3 G 1v2 G 3v3 G 1v2 G 3v3 G 1v2 G 3v3 G G ? ? ?
D1 D2 D3 3v3 G 3v3 G 3v3 G 3v3 G 3v3 G 3v3 G 3v3 G 3v3 G 1v2 1v2 ? ? ?
CMD 1v2 1v2 G 1v2 G 1v8 ? ? ?
? ? ? G G 3v3 G 1v8 G ? ? ?
? ? 3v3 3v3 G 1v2 G 1v2 ? ? ?
1v2 G 3v3 G 1v8 1v8 ? ? ?
G 1v2 G 1v8 G G ? ? ?
SCL 3v3 G 3v3 G 1v2 1v2 ? ? ?
SDA 1v2 3v3 G 1v8 G 1v8 ? ? ?
? ? G G 1v2 G 1v8 G ? ?
? ? ? 1v8 1v2 G 1v8 G 1v2 ? ?
? ? ? 1v2 G 1v8 G 1v2 1v8 ? ? ?
? ? ? G 1v8 G 1v8 G G ? ? ?
? ? ? 1v8 G 1v8 G 1v8 1v2 ? ? ?
G ? ? 1v2 1v2 G 1v8 G 1v8 G 1v8 G 1v2 G 1v8 G 1v8 G 1v8 G 1v8 ? ? ?
? ? ? G G 1v8 G 1v2 G 1v8 G 1v2 G 1v8 G 1v2 G 1v8 G 1v2 G ? ? ?
? ? ? 1v8 1v2 ? ? ?
? ? ? 1v2 1v8 ? ? ?
? ? ? G 1v8 1v2 G 1v8 1v2 G 1v8 1v2 G 1v8 1v2 G 1v8 1v2 G 1v8 1v2 G 1v8 1v2 G ? ? ?
? ? ? ? ? ? ? ? ? ? 3? 4? 5? B PADR PADD G ? ? G ? ? ? ?
? ? ? ?
G G ? ? ? ? ? ? ? ? SDA 1? 2? A STRT PADU L Y ? ? ? ? ? ? ?
G ? ? ? ? ? ? ? ? SCL 0? SLCT PADL R X ? ? ? ? ? ? G

legend:

SoC clock crystal
RTC clock crystal
Gamecard
SDCARD SDIO
NAND SDIO
WIFI SDIO
SPI
I2C-1
I2C-2
I2C-3
Pad
FCRAM
Camera
WIFI
GPIO
LCD0 (small)
LCD1 (big)
CODEC0 (unknown)
CODEC1 (unknown)
MCU (unknown)
POWER
Ground

Orientation: Triangle bottom right on the PCB.

UC CTR[edit]

The MCU seems to most closely resemble an NEC (Renesas) 78K0R/Kx3-L 64-pin FBGA: https://www.renesas.com/us/en/document/mah/78k0rkx3-l-users-manual-hardware-r01uh0106ej040078k0rkx3l?language=en&r=1051991

The functional pin mapping is almost exactly the same, except the GPIO port assignment is almost completely different.

Most low port numbers appear to map to the correct physical pin locations as described in the above datasheet, however around P7 and above this mapping is definitely altered.

Orientation: Pin 1 marker in bottom left corner

Pinout[edit]

8 + G TP75 X X ?
7 SCL G /RESET ? ? +
6 SDA + TP77 TP76 +
5 ? TP78 PWRLED1 CHRGLED
4 G G
3 PWRBTN BATTTHM
2 PWRLED0 HOMEBTN
1 + SCL SDA G
/ A B C D E F G H

Pin assignment[edit]

und = undocumented / custom
SFR = Special Function Register (SFR bank 1, range FFF00h - FFFFFh)
ESR = Extended Special Function Register (SFR bank 2, range F0000h - F0806h)
/   = active low (ground to enable, pull to power supply to disable)
TP Pin Port Purpose
TP79 A8 EVdd Digital voltage source input (positive)
TP74 E7 /RESET Resets the MCU when grounded, but is also used when reprogramming
TP75 E8 FLMD0 Flash mode(?) used when reprogramming with external programmer
TP76 E6 TOOL1 Used when using an ICE or debugger
TP77 D6 TOOL0 Multipurpose pin for reprogramming and debugging
A7 SCL0 / P6.0 DSi-side I2C SCL
A6 SDA0 / P6.1 DSi-side I2C SDA
E1 SCL1 / ESR[510h].und 3DS-side SCL
F1 SDA1 / ESR[510h].und 3DS-side SDA
F7 /P0.1 SocReset_n (one of the two SoC reset signals)
G7 /P0.0 SocReset_n (one of the two SoC reset signals)
/P3.0 Unknown. Probably resets something, as it's poked in a similar pattern to the SoC reset signals.
P5.0 Toggles something (poked in conjunction with reset signals)
P2.0 HOME button
P4.3 Charging LED(?)
P5.1 Charger "button"
P7.0 ???
P2.4 BatteryChargeState (?)
P7.3 Power button
P7.4 WiFi button
P7.6 External IRQ (MCU --> SoC)

CODEC[edit]

4? 3v3 3? 0? ? ? G
3? 5? G 1? CSx ? G
G 2? 0? G 2? CSy SPEAKER1
TOUCH TOUCH 1? G G G G G G SPEAKER1
TOUCH TOUCH G G G G G G
CPAD CPAD G G G G G G
G G G G G G SPEAKER2
MIC G G G G G G G SPEAKER2
JACK_R G G G G
3v3 G G G G
G JACK_L G G

LCD (old3DS bottom)[edit]

Pin number Name Description
01 -6V
02 12V
03 CLK Pixel clock
04 /HBL Horizontal blank (low while blanking)
05 /VBL Vertical blank (low while blanking)
06 2v2 Loopback of pin 07?
07 2v2 Content latch? Shorting this to ground or to pin 06 will "lock" the screen memory while still allowing the screen to refresh itself.
08 GND "chassi" ground
09 HCL Horizontal clock
10 GND "chassi" ground
11 BIAS 1 Default ~ 4.5V - 4.8V; sets contrast
12 BIAS 2 Usually matches BIAS 1; sets "flicker"
13 ??? Might be a transistor? Shorted to ground if off, 2.36V if on.
14 6V
15 ??? Loopback of pin 14 ? Shorting this with pin 14 or ground will make the 3DS turn off with a harsh pop sound.
16 ??? ???
17 ??? ???
18

[...]

25

RED 0

[...]

RED 7

Red pixel bits
26 GND "chassi" ground
27

[...]

34

BLUE 7

[...]

BLUE 0

Blue pixel bits
35 GND "chassi" ground
36

[...]

43

GREEN 7

[...]

GREEN 0

Green pixel bits
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