SPICARD Registers: Difference between revisions
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| style="background: green" | Yes | | style="background: green" | Yes | ||
| | | [[#REG_SPICARDASSERT|REG_SPICARDASSERT]] | ||
| 0x1000D804 | | 0x1000D804 | ||
| 4 | | 4 | ||
| Line 73: | Line 73: | ||
| Trigger (0 = idle, 1 = busy) | | Trigger (0 = idle, 1 = busy) | ||
|} | |} | ||
== REG_SPICARDCNT == | |||
When deasserting the card, this registers is set to 0. Presumably contains 1 when the card is asserted. | |||
== REG_SPICARDSIZE == | == REG_SPICARDSIZE == | ||
Revision as of 20:35, 28 April 2017
Registers
| Old3DS | Name | Address | Width | Used by |
|---|---|---|---|---|
| Yes | REG_SPICARDCNT | 0x1000D800 | 4 | |
| Yes | REG_SPICARDASSERT | 0x1000D804 | 4 | |
| Yes | REG_SPICARDSIZE | 0x1000D808 | 4 | |
| Yes | REG_SPICARDFIFO | 0x1000D80C | 4 | |
| Yes | REG_SPICARDFIFOSTAT | 0x1000D810 | 4 | |
| Yes | ? | 0x1000D814 | 4 | |
| Yes | ? | 0x1000D818 | 4 | |
| Yes | ? | 0x1000D81C | 4 |
REG_SPICARDCNT
| BIT | DESCRIPTION |
|---|---|
| 5-0 | Baud Rate |
| 12 | Bus Mode |
| 13 | Transfer Mode (0 = read, 1 = write) |
| 15 | Trigger (0 = idle, 1 = busy) |
REG_SPICARDCNT
When deasserting the card, this registers is set to 0. Presumably contains 1 when the card is asserted.
REG_SPICARDSIZE
| BIT | DESCRIPTION |
|---|---|
| 31-0 | Transfer size |
REG_SPICARDFIFO
| BIT | DESCRIPTION |
|---|---|
| 31-0 | Data |
REG_SPICARDFIFOSTAT
| BIT | DESCRIPTION |
|---|---|
| 0 | FIFO Full (0 = not full, 1 = full) |