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Memory layout: Difference between revisions

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|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x00000000
| <code>0x00000000</code>
| 0x00010000
| <code>0x10000</code>
| Bootrom (super secret code/data @ 0x8000)
| Boot ROM (super secret code/data @ 0x8000)
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x00010000
| <code>0x10000</code>
| 0x00010000
| <code>0x10000</code>
| Bootrom mirror
| Boot ROM mirror
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x10000000
| <code>0x10000000</code>
|?
| ''Unknown''
| [[IO]] memory
| [[IO]] memory
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x17E00000
| <code>0x17E00000</code>
| 0x00002000
| <code>0x2000</code>
| MPCore private memory region
| MPCore private memory region


|-
|-
| style="background: red" | No
| style="background: red" | No
| 0x17E10000
| <code>0x17E10000</code>
| 0x00001000
| <code>0x1000</code>
| L2C-310 Level 2 Cache Controller (2MB)
| L2C-310 Level 2 Cache Controller (2MB)
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x18000000
| <code>0x18000000</code>
| 0x00600000
| <code>0x600000</code>
| VRAM (divided in two banks, VRAM and VRAMB)
| VRAM (divided in two banks, VRAM and VRAMB)
|-
|-
| style="background: red" | No
| style="background: red" | No
| 0x1F000000
| <code>0x1F000000</code>
| 0x00400000
| <code>0x400000</code>
| [[New_3DS]] additional memory
| [[New 3DS]] additional memory
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x1FF00000
| <code>0x1FF00000</code>
| 0x00080000
| <code>0x80000</code>
| DSP memory
| DSP memory
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x1FF80000
| <code>0x1FF80000</code>
| 0x00080000
| <code>0x80000</code>
| AXI WRAM
| AXI WRAM
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x20000000
| <code>0x20000000</code>
| 0x08000000
| <code>0x8000000</code>
| FCRAM
| FCRAM
|-
|-
| style="background: red" | No
| style="background: red" | No
| 0x28000000
| <code>0x28000000</code>
| 0x08000000
| <code>0x8000000</code>
| [[New_3DS]] FCRAM extension
| [[New 3DS]] FCRAM extension
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0xFFFF0000
| <code>0xFFFF0000</code>
| 0x00010000
| <code>0x10000</code>
| Bootrom mirror
| Boot ROM mirror
|}
|}


===0x17E10000===
===0x17E10000===
The 32bit register at 0x17E10000+0x100 only has bit0 set when, on New3DS, [[PTMSYSM:ConfigureNew3DSCPU]] was used with bit1 set for the input value(the L2 cache flag). All other bits in this register are normally all-zero. Therefore: bit0 set = new cache hardware enabled, clear = new cache hardware disabled(this bit is how the ARM11-kernel checks whether the additional cache hw is enabled).
The 32-bit register at <code>0x17E10000</code>+<code>0x100</code> only has bit 0 set when, on New 3DS, [[PTMSYSM:ConfigureNew3DSCPU]] was used with bit 1 set for the input value (the L2 cache flag). All other bits in this register are normally all-zero. Therefore, bit 0 set = new cache hardware enabled, bit 0 clear = new cache hardware disabled. This bit is how the ARM11 kernel checks whether the additional cache hardware is enabled).


To enable the additional cache hw, the following is used by the ARM11-kernel:
To enable the additional cache hardware, the following is used by the ARM11 kernel:
* Sets bit0 in 32bit register 0x17E10000+0x100.
* Sets bit 0 in 32-bit register <code>0x17E10000</code>+<code>0x100</code>.


To disable the additional cache hw, the following is used by the ARM11-kernel:
To disable the additional cache hardware, the following is used by the ARM11 kernel:
* Writes value 0xFFFF to 32bit register 0x17E10000+0x77C.
* Writes value <code>0xFFFF</code> to 32-bit register <code>0x17E10000</code>+<code>0x77C</code>.
* Waits for bit0 in 32bit register 0x17E10000+0x730 to become clear.
* Waits for bit 0 in 32-bit register <code>0x17E10000</code>+<code>0x730</code> to become clear.
* Writes value 0x0 to 32bit register 0x17E10000+0x0.
* Writes value <code>0x0<code> to 32-bit register <code>0x17E10000</code>+<code>0x0</code>.
* Clears bit0 in 32bit register 0x17E10000+0x100.
* Clears bit 0 in 32-bit register <code>0x17E10000</code>+<code>0x100</code>.


=== 0x1F000000 ([[New_3DS]]-only) ===
=== <code>0x1F000000</code> ([[New 3DS]] only) ===
This area is used by [[QTM Services]](starting at offset 0x200000, size 0x180000). This area is not accessible to the GPU on the old 3DS. The old 3DS and New 3DS GSP module has vaddr->physaddr conversion code for this entire region. On the New 3DS, only the first 0x200000-bytes (half of this memory) are accessible to the GPU.
This area is used by [[QTM Services]],starting at offset <code>0x200000</code>, size <code>0x180000</code>. This area is not accessible to the GPU on the old 3DS. The old 3DS and New 3DS GSP module has <code>vaddr-&gt;physaddr</code> conversion code for this entire region. On the New 3DS, only the first <code>0x200000</code> bytes (half of this memory) are accessible to the GPU.


== ARM9 ==
== ARM9 ==
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|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x00000000
| <code>0x00000000</code>
| 0x08000000
| <code>0x8000000</code>
| Instruction TCM, repeating each 0x8000 bytes.
| Instruction TCM, repeating each <code>0x8000</code> bytes.
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x01FF8000
| <code>0x01FF8000</code>
| 0x00008000
| <code>0x8000</code>
| Instruction TCM (Accessed by the kernel and process by this address)
| Instruction TCM (Accessed by the kernel and process by this address)
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x07FF8000
| <code>0x07FF8000</code>
| 0x00008000
| <code>0x8000</code>
| Instruction TCM (Accessed by bootrom by this address)
| Instruction TCM (Accessed by bootrom by this address)
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x08000000
| <code>0x08000000</code>
| 0x00100000
| <code>0x100000</code>
| ARM9-only internal memory (ARM7's internal regions are mapped here as well)
| ARM9-only internal memory (ARM7's internal regions are mapped here as well)
|-
|-
| style="background: red" | No
| style="background: red" | No
| 0x08100000
| <code>0x08100000</code>
| 0x00080000
| <code>0x80000</code>
| [[New_3DS]] ARM9-only extension, only enabled when a certain [[CONFIG_Registers|CONFIG]] register is set.
| [[New 3DS]] ARM9-only extension, only enabled when a certain [[CONFIG_Registers|CONFIG]] register is set.
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x10000000
| <code>0x10000000</code>
| 0x08000000
| <code>0x8000000</code>
| [[IO]] memory
| [[IO]] memory
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x18000000
| <code>0x18000000</code>
| 0x00600000
| <code>0x600000</code>
| VRAM (divided in two banks, VRAM and VRAMB)  
| VRAM (divided in two banks, VRAM and VRAMB)  
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x1FF00000
| <code>0x1FF00000</code>
| 0x00080000
| <code>0x80000</code>
| DSP memory
| DSP memory
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x1FF80000
| <code>0x1FF80000</code>
| 0x00080000
| <code>0x80000</code>
| AXI WRAM
| AXI WRAM
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0x20000000
| <code>0x20000000</code>
| 0x08000000
| <code>0x8000000</code>
| FCRAM
| FCRAM
|-
|-
| style="background: red" | No
| style="background: red" | No
| 0x28000000
| <code>0x28000000</code>
| 0x08000000
| <code>0x8000000</code>
| [[New_3DS]] FCRAM extension
| [[New 3DS]] FCRAM extension
|-
|-
| style="background: green" | Yes
| style="background: gre</code>en" | Yes
| 0xFFF00000
| <code>0xFFF00000</code>
| 0x00004000
| <code>0x4000</code>
| Data TCM (Mapped during bootrom)
| Data TCM (Mapped during boot ROM)
|-
|-
| style="background: green" | Yes
| style="background: green" | Yes
| 0xFFFF0000
| <code>0xFFFF0000</code>
| 0x00010000
| <code>0x10000</code>
| Bootrom, the main region is at +0x8000, which is disabled during system boot.
| Boot ROM, the main region is at +<code>0x8000</code>, which is disabled during system boot.
|}
|}


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