Difference between revisions of "SHA Registers"
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| Line 39: | Line 39: | ||
| 0-1 | | 0-1 | ||
| 0=Hash ready, 1=Normal, 2=Final Round | | 0=Hash ready, 1=Normal, 2=Final Round | ||
| + | |- | ||
| + | | 2 | ||
| + | | ? | ||
|- | |- | ||
| 3 | | 3 | ||
| Line 45: | Line 48: | ||
| 4-5 | | 4-5 | ||
| Mode (0=SHA256, 1=SHA224, 2=3=SHA1) | | Mode (0=SHA256, 1=SHA224, 2=3=SHA1) | ||
| + | |- | ||
| + | | 6 | ||
| + | | ? | ||
| + | |- | ||
| + | | 7 | ||
| + | | ? | ||
|- | |- | ||
| 8 | | 8 | ||
| Unknown. When set, the *entire* ARM9 hangs/crashes when attempting to read REG_SHA_IN. | | Unknown. When set, the *entire* ARM9 hangs/crashes when attempting to read REG_SHA_IN. | ||
| + | |- | ||
| + | | 9 | ||
| + | | ? | ||
| + | |- | ||
| + | | 10 | ||
| + | | ? | ||
|- | |- | ||
| 16 | | 16 | ||
Revision as of 01:26, 20 March 2015
Registers
| Old3DS | Name | Address | Width | Used by |
|---|---|---|---|---|
| Yes | SHA_CNT | 0x1000A000 | 4 | Boot9, Process9 |
| Yes | SHA_INPUTSZ | 0x1000A004 | 4 | Process9 |
| Yes | SHA_HASH | 0x1000A040 | 0x20 | Process9 |
| Yes | SHA_IN | 0x1000A080 | 0x40 | Boot9, Process9 |
SHA_CNT
| Bits | Description |
|---|---|
| 0-1 | 0=Hash ready, 1=Normal, 2=Final Round |
| 2 | ? |
| 3 | Output Endianess (0=Little endian, 1=Big endian) |
| 4-5 | Mode (0=SHA256, 1=SHA224, 2=3=SHA1) |
| 6 | ? |
| 7 | ? |
| 8 | Unknown. When set, the *entire* ARM9 hangs/crashes when attempting to read REG_SHA_IN. |
| 9 | ? |
| 10 | ? |
| 16 | Enable |
| 17 | 1 when FIFO expects read/write |
SHA_INPUTSZ
This reg contains the total size of the data written to REG_SHA_IN.
SHA_HASH
This reg contains the SHA* hash after the final round, and the internal state during normal rounds. It is possible to write the internal state using this register.
SHA_IN
The data to be hashed must be written here. The data must be padded with 0x00s to align with the register size (if needed).